Patents by Inventor Jay S. Chun

Jay S. Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Implementing state-of-the-art gate transistor, sidewall profile/angle control by tuning gate etch process recipe parameters
    Patent number: 8709951
    Abstract: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: April 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Jay S. Chun
  • IMPLEMENTING STATE-OF-THE-ART GATE TRANSISTOR, SIDEWALL PROFILE/ANGLE CONTROL BY TUNING GATE ETCH PROCESS RECIPE PARAMETERS
    Publication number: 20090023293
    Abstract: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Inventor: Jay S. Chun