Abstract: Systems and methods for error detection and correction with integrity checking are provided. A method includes first processing both data vector bit values and integrity vector bit values using a single error correction and double error detection (SECDED) code to generate check bit values, where the SECDED code is configured to allow both: (1) a detection and correction of a single error in the data vector values, or (2) an indication of an uncorrectable error, where the uncorrectable error corresponds to more than a single error in the data vector bit values or a single error or a multi-bit error in the integrity vector bit values. The method further includes second processing the check bit values and indicating an uncorrectable error for more than a single error in the data vector bit values or for a single error or a multi-bit error in the integrity vector bit values.

Abstract: Systems and methods for error detection and correction with integrity checking are provided. A method includes first processing both data vector bit values and integrity vector bit values using a single error correction and double error detection (SECDED) code to generate check bit values, where the SECDED code is configured to allow both: (1) a detection and correction of a single error in the data vector values, or (2) an indication of an uncorrectable error, where the uncorrectable error corresponds to more than a single error in the data vector bit values or a single error or a multi-bit error in the integrity vector bit values. The method further includes second processing the check bit values and indicating an uncorrectable error for more than a single error in the data vector bit values or for a single error or a multi-bit error in the integrity vector bit values.

Abstract: A method and apparatus for determining integrated circuit layouts of a random access memory (RAM) from a virtual circuit description and specification of a process technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed in terms of reference points relative to a substrate surface. When the process technology is specified, the relationships among the reference points is determined, as in the layout of the RAM. These relationships account for variable sizing of circuit features and pitch matching of circuit features. A connectivity model and a simulation model of the RAM are also produced by the method and apparatus. These model can be used to verify that the RAM is connected as desired and has the desired performance.