Abstract: A pre-arbitrated bypassing system in a speculative execution microprocessor is provided. The bypassing system provides execution units enhanced to include a comparator and an enabled driver. The comparator compares a bypass address that is broadcast upon instruction decode with the destination address within each execution unit. If there is a match, then the result data is driven onto the bypass bus. Additionally, a suppress signal and validation scheme/apparatus are included to ensure that valid data is being driven onto the bypass bus. A bypass bus and associated apparatus may be included for every potential source operand.

Abstract: A pre-arbitrated bypassing system in a speculative execution microprocessor is provided. The bypassing system provides execution units enhanced to include a comparator and an enabled driver. The comparator compares a bypass address that is broadcast upon instruction decode with the destination address within each execution unit. If there is a match, then the result data is driven onto the bypass bus. Additionally, a suppress signal and validation scheme/apparatus are included to ensure that valid data is being driven onto the bypass bus. A bypass bus and associated apparatus may be included for every potential source operand.

Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected.

Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected.