Patents by Inventor Jay Sarkar

Jay Sarkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12625631
    Abstract: A processing device, operatively coupled with a memory device, determines a current workload characteristic of the memory device. The processing device further determines, by a trainable classifier processing the current workload characteristic, a first set of one or more parameter values that satisfies a threshold workload criterion associated with the memory device. The processing device further configures the firmware component of the memory device with the first set of one or more parameter values.
    Type: Grant
    Filed: July 16, 2024
    Date of Patent: May 12, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Sundararajan Sankaranarayanan, Ahmet Kaya, Josh Hieb, Jay Sarkar
  • Publication number: 20260127066
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including sending, to a device, log data comprising a first order of a set of error-handling operations to be performed on data residing in a segment of the memory device; receiving, from the device, a second order of the set of error-handling operations, wherein the second order is obtained by optimizing the log data, based on probability data of error recovery and latency data of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the second order on the data residing in the segment of the memory device.
    Type: Application
    Filed: January 6, 2026
    Publication date: May 7, 2026
    Inventors: Jay Sarkar, Ipsita Ghosh, Vamsi Pavan Rayaprolu
  • Publication number: 20260104799
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including obtaining a reordered set of error-handling operations, wherein the reordered set adjusts an order of one or more error-handling operations of an ordered set of error-handling operations to be performed to recover data residing in a segment of the memory device based on latency data for previously-performed error-handling operations, wherein the latency data for the previously-performed error-handling operations depends on a workload of the segment of the memory device; and performing one or more error-handling operations of the reordered set of error-handling operations on the data residing in the segment of the memory device.
    Type: Application
    Filed: December 17, 2025
    Publication date: April 16, 2026
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Patent number: 12530123
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device.
    Type: Grant
    Filed: May 16, 2024
    Date of Patent: January 20, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Patent number: 12524291
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including selecting sample data residing in the memory device; running a test on the sample data regarding a set of error-handling operations; and generating log data comprising a first order of the set of error-handling operations to be performed on data residing in a segment of the memory device.
    Type: Grant
    Filed: April 10, 2024
    Date of Patent: January 13, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Jay Sarkar, Ipsita Ghosh, Vamsi Pavan Rayaprolu
  • Publication number: 20250181134
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including providing current workload data of the memory device as input to a machine learning model, wherein the machine learning model is trained, using a plurality of workload data, to identify one or more power-saving parameters associated with each workload data of the plurality of workload data. The processing device can perform operations further including obtaining an output of the machine learning model, the output comprising the one or more power-saving parameters associated with the current workload data. The processing device can perform operations further including adjusting, based on the one or more power-saving parameters associated with the current workload data, a power state of the memory device.
    Type: Application
    Filed: November 25, 2024
    Publication date: June 5, 2025
    Inventors: Seyhan Karakulak, David Scott Ebsen, Saeed Sharifi Tehrani, Jay Sarkar
  • Publication number: 20250117137
    Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including identifying a set of logical addresses associated with data stored on the memory devices in one or more blocks of a first type; determining a temporal metric class associated with the set of logical addresses, wherein the temporal metric class is associated with a corresponding range of predicted update characteristic of the data; identifying, based on the temporal metric class, a set of blocks of a second type, wherein a first block of the first type comprises a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type comprises a second plurality of memory cells having a second number of bits per cell that exceeds the first number of bits per cell; and moving the data to the identified set of blocks.
    Type: Application
    Filed: October 3, 2024
    Publication date: April 10, 2025
    Inventors: Jay Sarkar, David Scott Ebsen, Aaron Lucas, Seyhan Karakulak, Saeed Sharifi Tehrani
  • Publication number: 20250028466
    Abstract: A processing device, operatively coupled with a memory device, determines a current workload characteristic of the memory device. The processing device further determines, by a trainable classifier processing the current workload characteristic, a first set of one or more parameter values that satisfies a threshold workload criterion associated with the memory device. The processing device further configures the firmware component of the memory device with the first set of one or more parameter values.
    Type: Application
    Filed: July 16, 2024
    Publication date: January 23, 2025
    Inventors: Aswin Thiruvengadam, Sundararajan Sankaranarayanan, Ahmet Kaya, Josh Hieb, Jay Sarkar
  • Patent number: 12181961
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for autonomously adapting data storage system performance, lifetime, capacity and/or operational requirements. A data storage system may comprise a controller and one or more non-volatile memory devices. The controller is configured to determine a category for a workload of one or more operations being processed by the data storage system using a machine-learned model. The controller is configured to determine an expected degradation of the one or more non-volatile memory devices. The controller is configured to adjust, based on the expected degradation and an actual usage of physical storage of the data storage system by a host system, an amount of physical storage of the data storage system available to the host system.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: December 31, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Jay Sarkar, Cory Peterson
  • Publication number: 20240379028
    Abstract: An interchangeable custom covering system (ICCS) for personal items such as caps, backpacks, handbags, watches, footwear, belts and cell phone cases etc. is disclosed. The system is comprised of a transparent, custom-fitted, flexible window that affixes to multiple articles and accessories to display personalized messages and graphics. For example, a user can obtain the customized window, create a team logo, print it out on a card and insert said card into the window affixed to a product such as a baseball cap. Other embodiments can include said cards having a multitude of shapes, sizes, colors, patterns and text thereon that significantly change the appearance of a product.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Inventor: Jay Sarkar
  • Publication number: 20240302968
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Publication number: 20240256375
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including selecting sample data residing in the memory device; running a test on the sample data regarding a set of error-handling operations; and generating log data comprising a first order of the set of error-handling operations to be performed on data residing in a segment of the memory device.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Inventors: Jay Sarkar, Ipsita Ghosh, Vamsi Pavan Rayaprolu
  • Patent number: 12019874
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Patent number: 11994936
    Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 28, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jay Sarkar, Ipsita Ghosh, Vamsi Pavan Rayaprolu
  • Publication number: 20240070008
    Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Jay Sarkar, Ipsita Ghosh, Vamsi Pavan Rayaprolu
  • Publication number: 20240053893
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Jay Sarkar, Vamsi Pavan Rayaprolu, Ipsita Ghosh
  • Publication number: 20230232933
    Abstract: An improved customizable shoe system that enables a wearer to personalize their shoes. The system includes a shoe including a sole and an upper extending about edges of the sole, and one or more transparent enclosures disposed about the shoe. The one or more enclosures each include an opening. A sheet containing one or more inserts corresponding in size and shape to the one or more enclosures, such that a user can remove the one or more inserts to be housed within the one or more enclosures.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Inventors: Jay Sarkar, Saikrishna Chatakondu
  • Publication number: 20230024176
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for autonomously adapting data storage system performance, lifetime, capacity and/or operational requirements. A data storage system may comprise a controller and one or more non-volatile memory devices. The controller is configured to determine a category for a workload of one or more operations being processed by the data storage system using a machine-learned model. The controller is configured to determine an expected degradation of the one or more non-volatile memory devices. The controller is configured to adjust, based on the expected degradation and an actual usage of physical storage of the data storage system by a host system, an amount of physical storage of the data storage system available to the host system.
    Type: Application
    Filed: October 4, 2022
    Publication date: January 26, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Jay SARKAR, Cory PETERSON
  • Patent number: 11538539
    Abstract: Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jay Sarkar, Cory Peterson, Amir Sanayei, Vidyabhushan Mohan, Yao Zhang
  • Patent number: 11531590
    Abstract: A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality. The method further includes comparing the uncorrected data with the data and metadata from the other storage devices, speculatively modifying the uncorrected data based, at least in part, on the other data to create a set of reconstructed first data codewords, and, in response to a determination that one of the reconstructed first data codewords has recovered the first data, issuing a write_raw command to rewrite the modified data and associated metadata to the first storage device.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: December 20, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Lee Helmick, Cory James Peterson, Jay Sarkar