Patents by Inventor Jay Schleicher
Jay Schleicher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170322775Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.Type: ApplicationFiled: May 22, 2017Publication date: November 9, 2017Inventors: Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan, Henry Kim
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Patent number: 9658830Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.Type: GrantFiled: June 30, 2014Date of Patent: May 23, 2017Assignee: Altera CorporationInventors: Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan, Henry Kim
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Patent number: 8788550Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.Type: GrantFiled: June 12, 2009Date of Patent: July 22, 2014Assignee: Altera CorporationInventors: Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan, Henry Kim
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Patent number: 7573297Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.Type: GrantFiled: December 11, 2006Date of Patent: August 11, 2009Assignee: Altera CorporationInventors: Guu Lin, Stephanie Tran, Bruce Pederson, Brad Vest, Jim Park, Jay Schleicher
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Patent number: 7558812Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.Type: GrantFiled: November 26, 2003Date of Patent: July 7, 2009Assignee: Altera CorporationInventors: Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan, Henry Kim
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Patent number: 7161384Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.Type: GrantFiled: July 12, 2005Date of Patent: January 9, 2007Assignee: Altera CorporationInventors: Guu Lin, Stephanie Tran, Bruce Pederson, Brad Vest, Jim Park, Jay Schleicher
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Patent number: 6927601Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.Type: GrantFiled: November 21, 2002Date of Patent: August 9, 2005Assignee: Altera CorporationInventors: Guu Lin, Stephanie Tran, Bruce Pederson, Brad Vest, Jim Park, Jay Schleicher