Patents by Inventor Jay Scott Fuller
Jay Scott Fuller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230198746Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Avdhesh CHHODAVDIA, Ling Tony CHEN, Felix Stefan DOMKE, Kambiz RAHIMI, Jay Scott FULLER
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Patent number: 11595189Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.Type: GrantFiled: October 27, 2020Date of Patent: February 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Avdhesh Chhodavdia, Ling Tony Chen, Felix Stefan Domke, Kambiz Rahimi, Jay Scott Fuller
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Publication number: 20220131686Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Avdhesh CHHODAVDIA, Ling Tony CHEN, Felix Stefan DOMKE, Kambiz RAHIMI, Jay Scott FULLER
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Patent number: 11184164Abstract: Disclosed is a cryptographic key management system implemented in access and tamper resistant circuitry. The circuitry includes processing circuitry to perform cryptographic processing based cryptographic keys. Cryptographic key registers include key portions and attribute portions. An interface receives commands from exposed circuitry that controls the processing circuitry to perform cryptographic processing based on the keys and associated attributes. The attributes indicate what operations may be performed on, or using, the associated keys. of the associated keys. The attributes indicate intended uses of the keys.Type: GrantFiled: February 2, 2018Date of Patent: November 23, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Kambiz Rahimi, Jay Scott Fuller, Ling Tony Chen, Felix Stefan Domke
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Publication number: 20190245686Abstract: Disclosed is a cryptographic key management system implemented in access and tamper resistant circuitry. The circuitry includes processing circuitry to perform cryptographic processing based cryptographic keys. Cryptographic key registers include key portions and attribute portions. An interface receives commands from exposed circuitry that controls the processing circuitry to perform cryptographic processing based on the keys and associated attributes. The attributes indicate what operations may be performed on, or using, the associated keys. of the associated keys. The attributes indicate intended uses of the keys.Type: ApplicationFiled: February 2, 2018Publication date: August 8, 2019Inventors: Kambiz Rahimi, Jay Scott Fuller, Ling Tony Chen, Felix Stefan Domke
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Patent number: 9678896Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.Type: GrantFiled: October 26, 2015Date of Patent: June 13, 2017Assignee: Certicom Corp.Inventors: Daniel Francis O'Loughlin, Keelan Smith, Jay Scott Fuller, William Lundy Lattin, Marinus Struik, Yuri Poeluev, Matthew John Campagna, Thomas Rudolf Stiemerling, Wei Cheng Joseph Ku
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Publication number: 20160048462Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.Type: ApplicationFiled: October 26, 2015Publication date: February 18, 2016Applicant: CERTICOM CORP.Inventors: Daniel Francis O'Loughlin, Keelan Smith, Jay Scott Fuller, William Lundy Lattin, Marinus Struik, Yuri Poeluev, Matthew John Campagna, Thomas Rudolf Stiemerling, Wei Cheng Joseph Ku
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Patent number: 9183158Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.Type: GrantFiled: December 26, 2013Date of Patent: November 10, 2015Assignee: Certicom Corp.Inventors: Daniel Francis O'Loughlin, Keelan Smith, Jay Scott Fuller, William Lundy Lattin, Marinus Struik, Yuri Poeluev, Matthew John Campagna, Thomas Rudolf Stiemerling, Weicheng Joseph Ku
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Patent number: 9143325Abstract: A non-linear transformation including a plurality of non-linear logical operations is masked to a second or higher order. The masking includes receiving a set of random bits, and machine-masking two or more of the plurality of non-linear logical operations with a same random bit from the set of random bits.Type: GrantFiled: December 14, 2012Date of Patent: September 22, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Zhimin Chen, Jay Scott Fuller
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Publication number: 20140169553Abstract: A non-linear transformation including a plurality of non-linear logical operations is masked to a second or higher order. The masking includes receiving a set of random bits, and machine-masking two or more of the plurality of non-linear logical operations with a same random bit from the set of random bits.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: MICROSOFT CORPORATIONInventors: Zhimin Chen, Jay Scott Fuller
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Publication number: 20140108825Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Inventors: Daniel Francis O'Loughlin, Keelan Smith, Jay Scott Fuller, William Lundy Lattin, Marinus Struik, Yuri Poeluev, Matthew John Campagna, Thomas Rudolf Stiemerling, Weicheng Joseph Ku
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Patent number: 8635467Abstract: An integrated circuit comprises logic circuitry, organized in a multi-level hierarchy of modules. The integrated circuit comprises multiple sensing circuits. In operation, each sensing circuit senses an instantaneous current consumption IC of a respective one of the modules that draws current entirely through that sensing circuit. The integrated circuit comprises a concealing circuit for each of the sensing circuits. In operation, the concealing circuit receives as input a voltage VC corresponding to the sensed instantaneous current consumption IC of its respective module, and the concealing circuit dissipates an instantaneous power PL such that an instantaneous power sum PTOTAL of the instantaneous power PL and the instantaneous power PC to be dissipated by its respective module is substantially independent of activity of its respective module.Type: GrantFiled: October 27, 2011Date of Patent: January 21, 2014Assignee: Certicom Corp.Inventors: Kiran Kumar Gunnam, Jay Scott Fuller
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Patent number: 8631247Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.Type: GrantFiled: November 24, 2009Date of Patent: January 14, 2014Assignee: Certicom Corp.Inventors: Daniel O'Loughlin, Keelan Smith, Jay Scott Fuller, Joseph Ku, William Lattin, Marinus Struik, Yuri Poeluev, Matthew J. Campagna, Thomas Stiemerling
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Publication number: 20130111224Abstract: An integrated circuit comprises logic circuitry, organized in a multi-level hierarchy of modules. The integrated circuit comprises multiple sensing circuits. In operation, each sensing circuit senses an instantaneous current consumption IC of a respective one of the modules that draws current entirely through that sensing circuit. The integrated circuit comprises a concealing circuit for each of the sensing circuits. In operation, the concealing circuit receives as input a voltage VC corresponding to the sensed instantaneous current consumption IC of its respective module, and the concealing circuit dissipates an instantaneous power PL such that an instantaneous power sum PTOTAL of the instantaneous power PL and the instantaneous power PC to be dissipated by its respective module is substantially independent of activity of its respective module.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: CERTICOM CORP.Inventors: Kiran Kumar GUNNAM, Jay Scott FULLER
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Patent number: 8334705Abstract: An integrated circuit comprises logic circuitry driven by a clock and reference circuitry. In operation, logic elements of the reference circuitry are synchronized to the clock. In operation, a first sensing circuit outputs a voltage VC proportional to an instantaneous current consumption IC of the logic circuitry, and a second sensing circuit outputs a voltage VR proportional to an instantaneous fluctuating current consumption IR of the reference circuitry. In operation, differential circuitry outputs a voltage difference ?VR?VC between a scaled-up version ?VR of the voltage VR and the voltage VC, the scaled-up version scaled to approximately the scale of the voltage VC. In operation, a square root circuit receives the voltage difference as input and outputs a square root of the voltage difference. A current source is controllable by the output of the square root circuit to generate current through a dissipative load.Type: GrantFiled: October 27, 2011Date of Patent: December 18, 2012Assignee: Certicom Corp.Inventors: Kiran Kumar Gunnam, Jay Scott Fuller
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Patent number: 8319533Abstract: There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.Type: GrantFiled: June 26, 2012Date of Patent: November 27, 2012Assignee: Certicom Corp.Inventor: Jay Scott Fuller
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Publication number: 20120268174Abstract: There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Applicant: CERTICOM CORP.Inventor: Jay Scott FULLER
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Patent number: 8228099Abstract: A system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.Type: GrantFiled: May 12, 2011Date of Patent: July 24, 2012Assignee: Certicom Corp.Inventor: Jay Scott Fuller
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Publication number: 20120102334Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.Type: ApplicationFiled: November 24, 2009Publication date: April 26, 2012Applicant: CERTICOM CORP.Inventors: Daniel O'Loughlin, Keelan Smith, Jay Scott Fuller, Joseph Ku, William Lattin, Marinus Struik, Yuri Poeluev, Martthew J. Campagna, Thomas Stiemerling
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Publication number: 20110210770Abstract: There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.Type: ApplicationFiled: May 12, 2011Publication date: September 1, 2011Applicant: CERTICOM CORP.Inventor: Jay Scott FULLER