Abstract: In a computer system having a CPU coupled to a memory wherein the memory is logically divided into a number of logical units, each having a number of memory words, a free memory block header list having a number of free memory block headers, one for each free memory block of a memory pool having a number of the memory words, is provided for tracking free memory blocks in the memory pool. The free memory block headers are organized as a Cartesian binary tree. The free memory block header list is used and maintained to control dynamic allocation and deallocation of free and allocated memory blocks of the memory pool. The memory pool is designed to have a memory pool size in multiples of the memory's logical units. All memory requests are rounded to multiples of the memory's word size. As a result, free and allocated memory blocks of the memory pool may be dynamically allocated and deallocated independent of how the memory is addressed, in particular, whether the memory is virtually or statically addressed.

Abstract: A field programmable gate array in which the pattern of a first smaller switch matrix is continued into a number of other smaller reduced switch matrices necessary to provide full coverage for all of the input conductor combinations at the output conductors.

Abstract: An integrated circuit including a plurality of individual boundary scan circuits each associated with a separate portion of the circuitry of the integrated circuit. The registers of the individual boundary scan circuits are joined to provide a series boundary scan register chain in which individual portions of the circuitry included within the integrated circuit may be individually manipulated.

Abstract: An integrated circuit including a plurality of individual boundary scan circuits each associated with a separate portion of the circuitry of the integrated circuit. The registers of the individual boundary scan circuits are joined to provide a series boundary scan register chain in which individual portions of the circuitry included within the integrated circuit may be individually manipulated.