Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.

Abstract: An apparatus and methods of making an electronic assembly. The electronic assembly comprises a functional block having at least one asymmetric feature. The functional block comprises an integrated circuitry to perform a function pertaining to the electronic assembly. The electronic assembly further comprises a substrate having a receptor site to mate with the functional block using a fluidic self-assembly process.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.