Abstract: A circuit for use in a digital data receiver to recover a clock signal, of variable rate, from the signal received by the receiver. A typical digital data receiver includes demodulating or other means for converting the received signal to a binary data signal having a characteristic which changes in a manner corresponding to transition in the digital data received. The invention provides circuit means for recovering a clock signal from the binary data signal where the data rate may vary over a substantial range. The clock signal recovery circuit utilizes a logic transition detector to produce a narrow pulse at each data transition in the binary data signal. The pulses, which contain harmonic frequencies at the clock rate of the binary data signal, are up-converted or mixed with an electrical signal from a frequency synthesizer. The signal resulting from this up-conversion is filtered by a narrow-band filter to produce an electrical signal at a predetermined intermediate frequency.