Patents by Inventor Jay W. Strane

Jay W. Strane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067078
    Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
  • Publication number: 20190067079
    Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
    Type: Application
    Filed: November 16, 2017
    Publication date: February 28, 2019
    Inventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
  • Patent number: 9984935
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Patent number: 9984916
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Patent number: 9941134
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Publication number: 20170236717
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Publication number: 20170236756
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Patent number: 9666474
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Publication number: 20170125302
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Application
    Filed: January 6, 2017
    Publication date: May 4, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Publication number: 20170125286
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Patent number: 8685809
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Patent number: 8421077
    Abstract: A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sameer H. Jain, Carl J. Radens, Shahab Siddiqui, Jay W. Strane
  • Patent number: 8299455
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Publication number: 20120208332
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Publication number: 20120132966
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Application
    Filed: October 15, 2007
    Publication date: May 31, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Patent number: 8188574
    Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Mahender Kumar, Effendi Leobandung, Jay W. Strane
  • Patent number: 8101518
    Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
  • Publication number: 20110298017
    Abstract: A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameer H. Jain, Carl J. Radens, Shahab Siddiqui, Jay W. Strane
  • Patent number: 8039382
    Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
  • Patent number: 7790553
    Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Bachir Dirahoui, Jay W. Strane, Gregory G. Freeman