Abstract: An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first top transistor comprising a first source/drain (S/D) region and a first bottom transistor with a second S/D region. The first bottom transistor may be stacked directly below the first transistor. The semiconductor structure may also include a backside power delivery network (BSPDN) below the bottom transistor, a back-end-of-line (BEOL) metal level above the top transistor, and a first interlevel via electrically connecting a top of the first S/D region to the BSPDN.

Abstract: A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.

Abstract: A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

Abstract: A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

Abstract: A semiconductor device including a second nanosheet transistor stacked over a first nanosheet transistor is provided which accommodates for having source/drain separating dielectric layers and/or stacked source/drain regions having a wide variety of vertical heights. The wide variety of heights can be along the same source/drain canyon or across different source/drain canyons.

Abstract: Embodiments of present invention provide a method of forming backside contact. The method includes forming a set of gate stacks on top of a substrate; forming a first recess in the substrate between the set of gate stacks, the first recess having a triangle shape with a pointy bottom; forming a dielectric anchor at the pointy bottom of the first recess; with the dielectric anchor at the pointy bottom, performing a sigma etch of the substrate through the first recess to form a second recess; epitaxially growing a semiconductor material in the second recess to form a placeholder for a backside contact; surrounding the placeholder with a dielectric material; and replacing the placeholder with a conductive material to form the backside contact. The semiconductor structure formed thereby is also provided.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

Abstract: A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.

Abstract: A device comprises a stacked transistor structure, and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, and a second metal gate structure of the second transistor. The second metal gate structure is embedded in the first metal gate structure.

Abstract: A device comprises a stacked transistor structure and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and which is disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, a second metal gate structure of the second transistor, and a metallic connection layer. The second metal gate structure is embedded in the first metal gate structure with a dielectric layer disposed between the first metal gate structure and the second metal gate structure. The metallic connection layer electrically connects upper regions of the first metal gate structure and the second metal gate structure.

Abstract: Embodiments of present invention provide a method of forming a transistor structure. The method includes forming a set of vertical fins on top of a substrate; forming a conformal spacer lining the set of vertical fins and the substrate; forming sidewall spacers next to vertical portions of the conformal spacer; removing portions of the conformal spacer on top of the substrate and between the sidewall spacers; indenting the conformal spacer vertically between the sidewall spacers and the substrate to create openings; forming bottom spacers in the openings; and forming a shallow-trench-isolation (STI) structure between the bottom spacers. A structure formed thereby is also provided.

Abstract: A semiconductor device is provided and includes a semiconductor substrate, a first nanosheet field effect transistor (FET) disposed on the semiconductor substrate, a second nanosheet FET stacked on the first nanosheet FET, dielectric material vertically interposed between the first nanosheet FET and the second nanosheet FET, bottom source/drain (S/D) epitaxy and top S/D epitaxy. The bottom S/D epitaxy contacts nanosheets of the first nanosheet FET. The bottom S/D epitaxy is formed from depositional overgrowth, chemical mechanical polishing (CMP) and recession processes and thereby includes a flat upper surface coplanar with a portion of the dielectric material. The top S/D epitaxy contacts nanosheets of the second nanosheet FET. The top S/D epitaxy is grown to have a shape differing from a shape of the bottom S/D epitaxy.

Abstract: A semiconductor device comprises a first nanosheet transistor structure, a second nanosheet transistor structure stacked on the first nanosheet transistor structure, and a semiconductor layer disposed between the first nanosheet transistor structure and the second nanosheet transistor structure. A first dielectric spacer is disposed around a first end portion of the semiconductor layer, and a second dielectric spacer disposed around a second end portion of the semiconductor layer. The second end portion of the semiconductor layer is disposed opposite the first end portion.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor IC structure includes an upper transistor and lower transistor each with respective source/drain (S/D) regions. The upper S/D region includes a S/D cut sidewall. A first frontside contact is in contact with the upper S/D region and includes a first conductive portion with a first cut sidewall that is substantially coplanar with the S/D cut sidewall. A second frontside contact is in contact with the lower S/D region and includes a second conductive portion with a second cut sidewall. A contact cut region may be between the first and second frontside contacts. This structure may be fabricated at least in part by forming a monolithic frontside contact against the lower S/D region and against the upper S/D region and simultaneously separating the monolithic frontside contact into the first frontside contact and the second frontside contact while removing a portion of the upper S/D region.

Abstract: A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source/drain (S/D) epitaxy and a bottom FET with bottom S/D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S/D epitaxy and cuts through the bottom S/D epitaxy with isolation between the backside contact and the bottom S/D epitaxy.

Abstract: VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked nanosheet structure and a second stacked nanosheet structure each including a first nanosheet structure formed at a first level and a second nanosheet structure formed at a second level. A configuration of the first stacked nanosheet structure on the first level is different than a configuration of the second stacked nanosheet structure on the first level, or the configuration of the first stacked nanosheet structure on the second level is different than a configuration of the second stacked nanosheet structure on the second level.

Abstract: A semiconductor structure is provided that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. Notably, the semiconductor structure includes a passive/diode device region including a lateral passive diode that is located between two nanosheet stacks. In embodiments, a logic device region including a stacked nanosheet transistor is located adjacent to the passive/diode device region.