Patents by Inventor Jaya Prakash Subramaniam Ganasan
Jaya Prakash Subramaniam Ganasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190324512Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipti Ranjan PAL
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Patent number: 10386904Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.Type: GrantFiled: March 31, 2016Date of Patent: August 20, 2019Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Christophe Denis Bernard Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik, Steven John Halter, Jaya Prakash Subramaniam Ganasan, Myil Ramkumar, Dipti Ranjan Pal
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Patent number: 9990291Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.Type: GrantFiled: September 24, 2015Date of Patent: June 5, 2018Assignee: QUALCOMM IncorporatedInventors: Hien Minh Le, Thuong Quang Truong, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez
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Patent number: 9921962Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.Type: GrantFiled: September 24, 2015Date of Patent: March 20, 2018Assignee: QUALCOMM IncorporatedInventors: Kun Xu, Thuong Quang Truong, Jaya Prakash Subramaniam Ganasan, Hien Minh Le, Cesar Aaron Ramirez
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Publication number: 20170285705Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipt Ranjan PAL
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Publication number: 20170091095Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: Kun Xu, Thuong Quang Truong, Jaya Prakash Subramaniam Ganasan, Hien Minh Le, Cesar Aaron Ramirez
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Publication number: 20170091098Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: Hien Minh Le, Thuong Quang Truong, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez
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Publication number: 20170075838Abstract: Techniques are disclosed to provide quality of service in bus interconnects with multi-stage arbitration. Source computing elements tag packets with a priority class and/or a number of credits that are based on a distance to a destination computing element of the packets. Arbiters controlling access to the bus interconnect perform arbitration operations to serve packets having higher relative priority based on the priority levels and/or numbers of credits of each packet.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Inventors: Prudhvi Nadh NOONEY, Jaya Prakash Subramaniam GANASAN
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Patent number: 9594713Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.Type: GrantFiled: September 12, 2014Date of Patent: March 14, 2017Assignee: QUALCOMM IncorporatedInventors: Randall John Pascarella, Jaya Prakash Subramaniam Ganasan, Thuong Quang Truong, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier
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Publication number: 20160246721Abstract: A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.Type: ApplicationFiled: February 19, 2015Publication date: August 25, 2016Inventors: Phil Joseph BOSTLEY, III, Jaya Prakash Subramaniam GANASAN
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Patent number: 9292442Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.Type: GrantFiled: July 2, 2013Date of Patent: March 22, 2016Assignee: QUALCOMM IncorporatedInventors: Thomas Philip Speier, Eric F. Robinson, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, James Norris Dieffenderfer
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Publication number: 20160077991Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Randall John Pascarella, Jaya Prakash Subramaniam Ganasan, Thuong Quang Truong, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier
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Patent number: 9286257Abstract: Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.Type: GrantFiled: January 28, 2011Date of Patent: March 15, 2016Assignee: QUALCOMM IncorporatedInventors: Richard Gerard Hofmann, Jaya Prakash Subramaniam Ganasan, Brandon Wayne Lewis
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Patent number: 9152595Abstract: Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements.Type: GrantFiled: October 18, 2012Date of Patent: October 6, 2015Assignee: QUALCOMM IncorporatedInventors: Jaya Prakash Subramaniam Ganasan, Mark Michael Schaffer, Prudhvi N. Nooney, Perry Willmann Remaklus, Jr.
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Publication number: 20150234761Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.Type: ApplicationFiled: May 7, 2015Publication date: August 20, 2015Inventors: Cristian Duroiu, Jaya Prakash Subramaniam Ganasan, Vinod Chamarty, Mark Michael Schaffer, Joshua Hirsch Stubbs, Robert Nicholson Gibson, Kris Tiri, Moinul Khan, Bohuslav Rychlik, Serag GadelRab, Simon Booth
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Patent number: 9064050Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.Type: GrantFiled: October 5, 2011Date of Patent: June 23, 2015Assignee: QUALCOMM IncorporatedInventors: Cristian Duroiu, Jaya Prakash Subramaniam Ganasan, Vinod Chamarty, Mark Michael Schaffer, Joshua H. Stubbs, Robert N. Gibson, Kris Tiri, Moinul H. Khan, Bohuslav Rychlik, Serag GadelRab, Simon Booth
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Patent number: 9026744Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.Type: GrantFiled: October 19, 2005Date of Patent: May 5, 2015Assignee: QUALCOMM IncorporatedInventors: Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Jaya Prakash Subramaniam Ganasan, James Norris Dieffenderfer, James Edward Sullivan
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Publication number: 20150074357Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache “hit” in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.Type: ApplicationFiled: March 3, 2014Publication date: March 12, 2015Applicant: QUALCOMM IncorporatedInventors: Joseph G. MCDONALD, Jaya Prakash Subramaniam GANASAN, Thomas Philip SPEIER, Eric F. ROBINSON, Jason Lawrence PANAVICH, Thuong Q. TRUONG
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Patent number: 8966291Abstract: A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same data in an unencoded format across the bus. The encoding method may be selected before transmission of the data across the bus, and may change depending on the data to be transmitted across the bus.Type: GrantFiled: December 23, 2010Date of Patent: February 24, 2015Assignee: QUALCOMM IncorporatedInventors: Jaya Prakash Subramaniam Ganasan, Martyn Ryan Shirlen
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Publication number: 20140310468Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.Type: ApplicationFiled: July 2, 2013Publication date: October 16, 2014Inventors: Thomas Philip Speier, Eric F. Robinson, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, James Norris Dieffenderfer