Patents by Inventor Jayachandra B. Avula

Jayachandra B. Avula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle
    Patent number: 5884060
    Abstract: An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: March 16, 1999
    Assignee: Ross Technology, Inc.
    Inventors: Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett, Yatin G. Mundkur, Vinay J. Naik, James E. Monaco
  • CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle
    Patent number: 5640588
    Abstract: An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: June 17, 1997
    Assignee: Ross Technology, Inc.
    Inventors: Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett, Yatin G. Mundkur, Vinay J. Naik, James E. Monaco
  • Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
    Patent number: 5488729
    Abstract: An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: January 30, 1996
    Assignee: Ross Technology, Inc.
    Inventors: Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett, Yatin G. Mundkur