Patents by Inventor Jayadeva

Jayadeva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12625677
    Abstract: A circuit for efficiently performing operations on input data to compute an interpretable and differentiable function, comprising a first level processing unit that obtains one or more first level inputs and a second level processing unit. The first level processing unit comprises (i) a first level MA unit that is configured to compute a first level weighted sum of the one or more first level inputs, and (ii) a logarithmic unit that is configured to compute a first level output. The second level processing unit obtains one or more second level inputs. The second level processing unit comprising (i) a second level MA unit that is configured to compute a second level weighted sum of the one or more second level inputs, and adding the computed second level product, and (ii) an antilog unit that is configured to compute a second level output.
    Type: Grant
    Filed: June 9, 2025
    Date of Patent: May 12, 2026
    Assignee: SPARSEMIND TECHNOLOGY LABS PRIVATE LIMITED
    Inventor: Jayadeva
  • Publication number: 20250377860
    Abstract: A circuit for efficiently performing operations on input data to compute an interpretable and differentiable function, comprising a first level processing unit that obtains one or more first level inputs and a second level processing unit. The first level processing unit comprises (i) a first level MA unit that is configured to compute a first level weighted sum of the one or more first level inputs, and (ii) a logarithmic unit that is configured to compute a first level output. The second level processing unit obtains one or more second level inputs. The second level processing unit comprising (i) a second level MA unit that is configured to compute a second level weighted sum of the one or more second level inputs, and adding the computed second level product, and (ii) an antilog unit that is configured to compute a second level output.
    Type: Application
    Filed: June 9, 2025
    Publication date: December 11, 2025
    Inventor: Jayadeva
  • Patent number: 11049011
    Abstract: Approaches for classifying training samples with minimal error in a neural network using a low complexity neural network classifier, are described. In one example, for the neural network, an upper bound on the Vapnik-Chervonenkis (VC) dimension is determined. Thereafter, an empirical error function corresponding to the neural network is determined. A modified error function based on the upper bound on the VC dimension and the empirical error function is generated, and used for training the neural network.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 29, 2021
    Assignee: Indian Institute of Technology Delhi
    Inventor: Jayadeva
  • Patent number: 10891559
    Abstract: Systems and methods for classifying binary data based training data having a predefined sample size is obtained. The training data is composed of separable binary datasets. An exact bound on Vapnik-Chervonenkis (VC) dimension of a classifier for the training data is determined. The exact bound is based one or more variables defining the hyperplane. The exact bound may be minimized for generating a classifier for predicting one class to which a given data sample of the training data belongs.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: January 12, 2021
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY DELHI
    Inventor: Jayadeva
  • Publication number: 20180144246
    Abstract: Approaches for classifying training samples with minimal error in a neural network using a low complexity neural network classifier, are described. In one example, for the neural network, an upper bound on the Vapnik-Chervonenkis (VC) dimension is determined. Thereafter, an empirical error function corresponding to the neural network is determined. A modified error function based on the upper bound on the VC dimension and the empirical error function is generated, and used for training the neural network.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 24, 2018
    Inventor: Jayadeva
  • Patent number: 8271281
    Abstract: Techniques for assessing pronunciation abilities of a user are provided. The techniques include recording a sentence spoken by a user, performing a classification of the spoken sentence, wherein the classification is performed with respect to at least one N-ordered class, and wherein the spoken sentence is represented by a set of at least one acoustic feature extracted from the spoken sentence, and determining a score based on the classification, wherein the score is used to determine an optimal set of at least one question to assess pronunciation ability of the user without human intervention.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: September 18, 2012
    Assignee: Nuance Communications, Inc.
    Inventors: Jayadeva, Sachindra Joshi, Himanshu Pant, Ashish Verma
  • Publication number: 20090171661
    Abstract: Techniques for assessing pronunciation abilities of a user are provided. The techniques include recording a sentence spoken by a user, performing a classification of the spoken sentence, wherein the classification is performed with respect to at least one N-ordered class, and wherein the spoken sentence is represented by a set of at least one acoustic feature extracted from the spoken sentence, and determining a score based on the classification, wherein the score is used to determine an optimal set of at least one question to assess pronunciation ability of the user without human intervention.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 2, 2009
    Applicant: International Business Machines Corporation
    Inventors: Jayadeva, Sachindra Joshi, Himanshu Pant, Ashish Verma
  • Publication number: 20030058149
    Abstract: The invention relates to an analog to digital converter computing all the bits in parallel or sequentially, without using decoding logic having an analog input and a digital output, wherein given the analog signal x, each bit can be computed by applying a formula containing a non linear periodic function which may be sine shaped or pulse shaped.
    Type: Application
    Filed: July 22, 2002
    Publication date: March 27, 2003
    Applicant: THE INDIAN INSTITUTE OF TECHNOLOGY (IItd)
    Inventor: Jayadeva