Patents by Inventor Jayaganasan Narayanasamy
Jayaganasan Narayanasamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145340Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Jayaganasan Narayanasamy, Angel Enverge, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Patent number: 11908771Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: GrantFiled: November 12, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Publication number: 20230154827Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Publication number: 20220278085Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.Type: ApplicationFiled: February 22, 2022Publication date: September 1, 2022Applicant: Infineon Technologies AGInventors: Chau Fatt CHIANG, Paul Armand Asentista CALO, Chan Lam CHA, Kok Yau CHUA, Chee Hong LEE, Swee Kah LEE, Theng Chao LONG, Jayaganasan NARAYANASAMY, Khay Chwan Andrew SAW
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Patent number: 11362023Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.Type: GrantFiled: July 12, 2019Date of Patent: June 14, 2022Assignee: Infineon Technologies AGInventors: Jayaganasan Narayanasamy, Meng How Chong, Elmer Senorin Holgado, Chee Ming Lam, Sanjay Kumar Murugan, Arivindran Navaretnasinggam, Kai Yang Tan, Lee Shuang Wang
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Publication number: 20220115245Abstract: A method for fabricating a power semiconductor package includes: providing a leadframe having a die pad and a frame, wherein the die pad is connected to the frame by at least one tie bar; attaching a semiconductor die to the die pad; laser cutting through the at least one tie bar, thereby forming a cut surface; and after the laser cutting, molding over the die pad and the semiconductor die, wherein the cut surface is completely covered by molding compound.Type: ApplicationFiled: October 4, 2021Publication date: April 14, 2022Inventors: Jayaganasan Narayanasamy, Syahir Abd Hamid, Meng How Chong, Michael Reyes Godoy, Chee Ming Lam, Adbul Rahman Mohamed, Sanjay Kumar Murugan, Thomas Stoek
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Publication number: 20220102263Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.Type: ApplicationFiled: August 27, 2021Publication date: March 31, 2022Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
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Patent number: 11274984Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: GrantFiled: June 2, 2020Date of Patent: March 15, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20210025774Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: ApplicationFiled: June 2, 2020Publication date: January 28, 2021Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20210013135Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.Type: ApplicationFiled: July 12, 2019Publication date: January 14, 2021Inventors: Jayaganasan Narayanasamy, Meng How Chong, Elmer Senorin Holgado, Chee Ming Lam, Sanjay Kumar Murugan, Arivindran Navaretnasinggam, Kai Yang Tan, Lee Shuang Wang
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Patent number: 10651109Abstract: A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.Type: GrantFiled: July 8, 2019Date of Patent: May 12, 2020Assignee: Infineon Technologies AGInventors: Syahir Abd Hamid, Jagen Krishnan, Mian Mian Lam, Jayaganasan Narayanasamy, Fabian Schnoy, Thomas Stoek, Christian Stuempfl
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Publication number: 20200020621Abstract: A semiconductor package having an electrically insulating mold compound body, a metal heat slug and a plurality of electrically conductive leads is provided. The heat slug has a rear surface that is exposed from the mold compound body and a die attach surface opposite the rear surface and to which a semiconductor die is mounted. each of the leads have outer portions that are exposed from the mold compound body. The outer portions of the leads are coated with a metal coating. After completing the coating of the outer portions of the leads, a planar metallic heat sink interface surface is provided on the semiconductor device. The planar metallic heat sink interface surface is exposed from the mold compound body, thermally coupled to the semiconductor die via the heat slug, and substantially devoid of the metal coating.Type: ApplicationFiled: July 16, 2018Publication date: January 16, 2020Inventors: Syahir Abd Hamid, Jagen Krishnan, Jayaganasan Narayanasamy
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Publication number: 20200020607Abstract: A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.Type: ApplicationFiled: July 8, 2019Publication date: January 16, 2020Inventors: Syahir Abd Hamid, Jagen Krishnan, Mian Mian Lam, Jayaganasan Narayanasamy, Fabian Schnoy, Thomas Stoek, Christian Stuempfl
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Patent number: 10457001Abstract: A method for forming a matrix composite layer on a workpiece and a workpiece with a matrix composite layer are disclosed. In an embodiment the method includes forming a wall around a metallic surface such that the wall extends in a vertical direction from a plane formed by the metallic surface, and depositing a filler material in a walled area on the metallic surface. The method further includes depositing a plastic material on the filler material and performing a vacuum treatment of the filler material and the plastic material thereby forming a matrix composite layer disposed on the metallic surface.Type: GrantFiled: April 3, 2018Date of Patent: October 29, 2019Assignee: Infineon Technologies AGInventors: Jayaganasan Narayanasamy, Jagen Krishnan, Sanjay Kumar Murugan, Hong Lim Lee
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Patent number: 10121723Abstract: According to an embodiment of a method, the method includes forming a first thermally conductive layer on an outer surface of a semiconductor package. The first thermally conductive layer formed on the outer surface of the semiconductor package is configured to be mounted to an external heat sink.Type: GrantFiled: April 13, 2017Date of Patent: November 6, 2018Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Kok Tee Lau, Jayaganasan Narayanasamy
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Publication number: 20180301390Abstract: According to an embodiment of a method, the method includes forming a first thermally conductive layer on an outer surface of a semiconductor package. The first thermally conductive layer formed on the outer surface of the semiconductor package is configured to be mounted to an external heat sink.Type: ApplicationFiled: April 13, 2017Publication date: October 18, 2018Inventors: Kok Tee Lau, Jayaganasan Narayanasamy
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Publication number: 20180297301Abstract: A method for forming a matrix composite layer on a workpiece and a workpiece with a matrix composite layer are disclosed. In an embodiment the method includes forming a wall around a metallic surface such that the wall extends in a vertical direction from a plane formed by the metallic surface, and depositing a filler material in a walled area on the metallic surface. The method further includes depositing a plastic material on the filler material and performing a vacuum treatment of the filler material and the plastic material thereby forming a matrix composite layer disposed on the metallic surface.Type: ApplicationFiled: April 3, 2018Publication date: October 18, 2018Inventors: Jayaganasan Narayanasamy, Jagen Krishnan, Sanjay Kumar Murugan, Hong Lim Lee