Abstract: A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

Abstract: A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

Abstract: A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

Abstract: A microcontroller includes a data memory configured to store test signal data. The microcontroller further includes a signal generator configured to process the test signal data in order to provide at least one test signal. The microcontroller also includes a circuit under test configured to process the test signal. The test signal data includes at least one pattern snippet and an associated pattern descriptor. The pattern snippet includes data concerning a content of a part of the test signal. The associated pattern descriptor includes data concerning a pattern formed by the pattern snippet within the test signal.

Abstract: In an embodiment, an apparatus includes: a fabric of a first communication protocol to communicate with an upstream agent in an upstream direction and to communicate with a plurality of downstream agents in a downstream direction; a switch coupled between the fabric and at least some of the plurality of downstream agents, the switch to couple to a primary interface of the fabric via a primary interface of the switch and to communicate with the fabric via the first communication protocol, the switch further including a sideband interface to interface with a sideband fabric of the first communication protocol; and the at least some downstream agents coupled to the switch via the sideband fabric, wherein the at least some downstream agents are to be enumerated with a secondary bus of a second communication protocol, and the switch device is to provide a transaction received from the upstream agent to a first downstream agent based on a bus identifier of the secondary bus with which the first downstream agent is

Abstract: A semiconductor chip, including an Intellectual Property (IP) core; and a signal forcing circuit located within the IP core, or located at a boundary of the IP core coupling the IP core with another IP core, the signal forcing circuit configured to: transmit an input signal received by the IP core as an output signal; and in response to a trigger condition, forcing an override signal as the output signal.

Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

Abstract: A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

Abstract: A microcontroller includes a data memory configured to store test signal data. The microcontroller further includes a signal generator configured to process the test signal data in order to provide at least one test signal. The microcontroller also includes a circuit under test configured to process the test signal. The test signal data includes at least one pattern snippet and an associated pattern descriptor. The pattern snippet includes data concerning a content of a part of the test signal. The associated pattern descriptor includes data concerning a pattern formed by the pattern snippet within the test signal.

Abstract: In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex including a first root port to interface to a first device to be coupled to the apparatus via a first interconnect and a second root port to interface to the agent via a bridge logic; and the bridge logic to interface the second root port to the agent, convert a first transaction from the first root port having a first format to a second format and communicate the first transaction having the second format to the agent. Other embodiments are described and claimed.

Abstract: A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

Abstract: In an embodiment, an apparatus includes: a fabric of a first communication protocol to communicate with an upstream agent in an upstream direction and to communicate with a plurality of downstream agents in a downstream direction; a switch coupled between the fabric and at least some of the plurality of downstream agents, the switch to couple to a primary interface of the fabric via a primary interface of the switch and to communicate with the fabric via the first communication protocol, the switch further including a sideband interface to interface with a sideband fabric of the first communication protocol; and the at least some downstream agents coupled to the switch via the sideband fabric, wherein the at least some downstream agents are to be enumerated with a secondary bus of a second communication protocol, and the switch device is to provide a transaction received from the upstream agent to a first downstream agent based on a bus identifier of the secondary bus with which the first downstream agent is

Abstract: An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.

Abstract: In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex including a first root port to interface to a first device to be coupled to the apparatus via a first interconnect and a second root port to interface to the agent via a bridge logic; and the bridge logic to interface the second root port to the agent, convert a first transaction from the first root port having a first format to a second format and communicate the first transaction having the second format to the agent. Other embodiments are described and claimed.

Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

Abstract: A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

Abstract: Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.

Abstract: An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.