Abstract: A method for self-ordering Fast Fourier Transform for Single Instruction Multiple Data engines includes performing a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector, the second input vector, the first output vector and the second output vector are each comprised of complex numbers, and a first order of the complex numbers of the first output vector is non-linear and a second order of the complex numbers of the second output vector is non-linear. A combination of complex numbers is reordered and exchanged between the first output vector and the second output vector to partially linearize the first order of the first output vector and to partially linearize the second order of the second output vector.

Abstract: Embodiments are disclosed that for synthetic aperture radar (SAR) systems and methods that process radar image data to generate radar images using vector processor engines, such as single-instruction-multiple-data (SIMD) processor engines. The vector processor engines can be further augmented with accelerators that vectorize element selection thereby expediting memory accesses required for interpolation operations performed by the vector processor engines.

Abstract: A processor including a pointer storage that stores pointer descriptors each including addressing information, an arithmetic logic unit (ALU) configured to execute an instruction which includes operand indexes each identifying a corresponding pointer descriptor, multiple address generation units (AGUs), each configured to translate addressing information from a corresponding pointer descriptors into memory addresses for accessing corresponding operands stored in a memory, and a smart cache. The smart cache includes a cache storage, and uses the memory addresses from the AGUs to retrieve and store operands from the memory into the cache storage, and to provide the stored operands to the ALU when executing the instruction. The smart cache replaces a register file used by a conventional processor for retrieving and storing operand information. The pointer operands include post-update capability that reduces instruction fetches. Wasted memory cycles associated with cache speculation are avoided.

Abstract: A method and apparatus (200A) are provided for multiplexing data and uplink control bitstreams on a 5G-NR uplink by generating a multiplexing configuration structure with one or more processors (201) and supplying the data and uplink control bitstreams to a multiplexing engine (214) which includes an index calculation logic circuit (212) and multiplex selector circuit (213), where the index calculation logic circuit is configured with the multiplexing configuration structure (CONFIG) to execute an iterative data-control multiplexing algorithm which generates ordered selection indices in sequential order (MUX_SEL), and where the multiplex selector circuit receives and selects m-bit sequences from the data bitstream and one or more uplink control bitstreams for output into a multiplexed output stream according to the ordered selection indices generated by the index calculation unit, where m is an integer greater than or equal to 1.

Abstract: Embodiments are disclosed that for synthetic aperture radar (SAR) systems and methods that process radar image data to generate radar images using vector processor engines, such as single-instruction-multiple-data (SIMD) processor engines. The vector processor engines can be further augmented with accelerators that vectorize element selection thereby expediting memory accesses required for interpolation operations performed by the vector processor engines.

Abstract: A mechanism is provided for detecting and decoding a primary broadcast channel transmitted by a base station at a user equipment device. Embodiments improve performance and robustness over prior methods for detecting and decoding by determining a channel differential metric for channel estimates derived based on each candidate demodulation reference symbol (DMRS) sequence and selecting a set of top DMRS sequence candidates using the associated channel differential metrics. From the set of top DMRS candidates, a best DMRS candidate, and consequently, the three least significant bits of the beam index, can be determined.

Abstract: A mechanism is provided for detecting and decoding a primary broadcast channel transmitted by a base station at a user equipment device. Embodiments improve performance and robustness over prior methods for detecting and decoding by determining a channel differential metric for channel estimates derived based on each candidate demodulation reference symbol (DMRS) sequence and selecting a set of top DMRS sequence candidates using the associated channel differential metrics. From the set of top DMRS candidates, a best DMRS candidate, and consequently, the three least significant bits of the beam index, can be determined.

Abstract: A base station is configured to provides a beam change feedback channel for a user equipment to communicate unsolicited beam change feedback to the base station. If the user equipment determines that a beam other than the beam to which the user equipment is tuned has a stronger signal, the user equipment initiates a transmission on the beam change feedback channel to the base station indicating a beam change. The base station uses the feedback from the user equipment to update the beam to the user equipment.

Abstract: A base station is configured to provides a beam change feedback channel for a user equipment to communicate unsolicited beam change feedback to the base station. If the user equipment determines that a beam other than the beam to which the user equipment is tuned has a stronger signal, the user equipment initiates a transmission on the beam change feedback channel to the base station indicating a beam change. The base station uses the feedback from the user equipment to update the beam to the user equipment.

Abstract: Digital pre-distortion is performed on a received signal using a set of pre-distortion coefficients to produce a digital pre-distorted signal. The digital pre-distorted signal is converted to an analog signal, which is amplified to produce a transmission output signal. The transmission output signal is converted to a digital feedback signal. A plurality of fractional delay filters is applied to the digital feedback signal to obtain a plurality of fractional delay compensated (FDC) candidates, and gain compensation is applied to each of the plurality of FDC candidates to obtain a plurality of gain and fractional delay compensated (XFT) candidates. The digital pre-distorted signal is used as a reference signal, and the XFT candidates and the reference signal are used to select a selected XFT candidate of the plurality of XFT candidates. The selected XFT candidate is used to generate the set of pre-distortion coefficients.

Abstract: In an RF transmitter, a digital predistortion circuit receives a sequence of input sample blocks, and performs a digital predistortion process to produce a predistorted output signal. The digital predistortion process includes selecting a set of predistortion coefficients for an input sample block from a plurality of different sets of predistortion coefficients. Each of the plurality of different sets of predistortion coefficients is associated with a different combination of one of a plurality of time slices within a radio frame and one of a plurality of power ranges. The selected set of predistortion coefficients is associated with a time slice within which the input sample block is positioned and a power range calculated for the input sample block based on block power statistics of the sample block. The process also includes applying the selected set of predistortion coefficients to the input sample block to produce the predistorted output signal.

Abstract: In an RF transmitter, a digital predistortion circuit receives a sequence of input sample blocks, and performs a digital predistortion process to produce a predistorted output signal. The digital predistortion process includes selecting a set of predistortion coefficients for an input sample block from a plurality of different sets of predistortion coefficients. Each of the plurality of different sets of predistortion coefficients is associated with a different combination of one of a plurality of time slices within a radio frame and one of a plurality of power ranges. The selected set of predistortion coefficients is associated with a time slice within which the input sample block is positioned and a power range calculated for the input sample block based on block power statistics of the sample block. The process also includes applying the selected set of predistortion coefficients to the input sample block to produce the predistorted output signal.

Abstract: A digital frontend circuit for a radio frequency (RF) comprises a digital predistortion (DPD) block, a plurality of sub-sample delay elements, and a selection circuit. The DPD block for computing predistorted transmit signals according to a Volterra series approximation model. The DPD block has an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate. Each of the sub-sample delay elements provides a delay to an input sample as specified by the Volterra series approximation model, where each of the delays is based on a fraction of the first sample rate. The selection circuit selects one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block. The selection signal for selecting a delay as specified by the Volterra series approximation model.