Patents by Inventor Jayakumaran Sivagnaname
Jayakumaran Sivagnaname has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8164942Abstract: Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.Type: GrantFiled: February 1, 2010Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Fadi H. Gebara, Jente B. Kuang, Jayakumaran Sivagnaname, Ivan Vo
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Publication number: 20110188295Abstract: Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.Type: ApplicationFiled: February 1, 2010Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi H. Gebara, Jente B. Kuang, Jayakumaran Sivagnaname, Ivan Vo
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Patent number: 7885798Abstract: A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.Type: GrantFiled: May 10, 2007Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Ying Liu, Sani R. Nassif, Jayakumaran Sivagnaname
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Patent number: 7760565Abstract: A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.Type: GrantFiled: July 24, 2007Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Jente B. Kuang, Jerry C. Kao, Hung C. Ngo, Kevin J. Nowka, Liang-Teck Pang, Jayakumaran Sivagnaname
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Patent number: 7751267Abstract: A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors.Type: GrantFiled: July 24, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida Kanj, Jayakumaran Sivagnaname
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Patent number: 7622942Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.Type: GrantFiled: June 26, 2008Date of Patent: November 24, 2009Assignee: International Business Machines CorporationInventors: Kanak B. Agarwal, Ying Liu, Chandler T. McDowell, Sani R. Nassif, James F. Plusquellic, Jayakumaran Sivagnaname
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Publication number: 20090251223Abstract: A method, system and computer program product for characterizing FET transistors in an electronic circuit (IC) device using Performance Screen Ring Oscillator (PSRO) techniques. During PSRO testing, logic and non-logic bias voltages are applied to gate terminals of the being tested FETs to determine process-related variations and the relative strength of N-type and P-type transistors.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: SANI R. NASSIF, JAYAKUMARAN SIVAGNANAME
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Publication number: 20090027065Abstract: A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Inventors: Jente B. Kuang, Jerry C. Keo, Hung C. Ngo, Kevin J. Nowka, Liang-Teck Pang, Jayakumaran Sivagnaname
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Publication number: 20090027983Abstract: A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Inventors: Rajiv V. Joshi, Rouwaida Kanj, Jayakumaran Sivagnaname
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Publication number: 20080284461Abstract: An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.Type: ApplicationFiled: June 18, 2008Publication date: November 20, 2008Inventors: Fadi H. Gebara, Ying Liu, Jayakumaran Sivagnaname, Ivan Vo
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Publication number: 20080281570Abstract: A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: Rajiv V. Joshi, Rouwaida N. Kanj, Ying Liu, Sani R. Nassif, Jayakumaran Sivagnaname
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Publication number: 20080258752Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.Type: ApplicationFiled: June 26, 2008Publication date: October 23, 2008Inventors: Kanak B. Agarwal, Ying Liu, Chandler T. McDowell, Sani R. Nassif, James F. Plusquellic, Jayakumaran Sivagnaname
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Patent number: 7408372Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.Type: GrantFiled: June 8, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Kanak B. Agarwal, Ying Liu, Chandler T. McDowell, Sani R. Nassif, James F. Plusquellic, Jayakumaran Sivagnaname
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Patent number: 7394276Abstract: An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.Type: GrantFiled: January 17, 2006Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Fadi H. Gebara, Ying Liu, Jayakumaran Sivagnaname, Ivan Vo
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Publication number: 20070296442Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.Type: ApplicationFiled: June 8, 2006Publication date: December 27, 2007Inventors: Kanak B. Agarwal, Ying Liu, Chandler T. McDowell, Sani R. Nassif, James F. Plusquellic, Jayakumaran Sivagnaname
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Publication number: 20070164769Abstract: An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Inventors: Fadi Gebara, Ying Liu, Jayakumaran Sivagnaname, Ivan Vo
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Patent number: 7129754Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.Type: GrantFiled: March 17, 2005Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Hung C. Ngo, Jayakumaran Sivagnaname, Kevin J. Nowka, Robert K. Montoye
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Publication number: 20060208763Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.Type: ApplicationFiled: March 17, 2005Publication date: September 21, 2006Inventors: Hung Ngo, Jayakumaran Sivagnaname, Kevin Nowka, Robert Montoye