Patents by Inventor Jayanthi Natarajan

Jayanthi Natarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ANTI-PAD FOR SIGNAL AND POWER VIAS IN PRINTED CIRCUIT BOARD
    Publication number: 20190037684
    Abstract: In one embodiment, an apparatus includes a plurality of layers in a printed circuit board comprising at least one power plane and at least one ground plane, and a plurality of vias extending through the plurality of layers and connecting two or more of the layers, the plurality of vias comprising at least one pair of differential signal vias and at least one pair of power vias, the signal vias and power vias surrounded by a plurality of ground vias. The ground plane includes an anti-pad formed therein by an opening defined by removal of material, with the pair of differential signal vias and pair of power vias extending through the anti-pad in the ground plane to reduce power via resonance.
    Type: Application
    Filed: July 26, 2017
    Publication date: January 31, 2019
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Il-Young Park, Jayanthi Natarajan
  • Anti-pad for signal and power vias in printed circuit board
    Patent number: 10194524
    Abstract: In one embodiment, an apparatus includes a plurality of layers in a printed circuit board comprising at least one power plane and at least one ground plane, and a plurality of vias extending through the plurality of layers and connecting two or more of the layers, the plurality of vias comprising at least one pair of differential signal vias and at least one pair of power vias, the signal vias and power vias surrounded by a plurality of ground vias. The ground plane includes an anti-pad formed therein by an opening defined by removal of material, with the pair of differential signal vias and pair of power vias extending through the anti-pad in the ground plane to reduce power via resonance.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Il-Young Park, Jayanthi Natarajan