Abstract: A clock divider receives a main clock and generates divided clocks (even or odd division) each having generally a half duty cycle. The clock divider includes flip flops connected to form a master-slave counter in which the master components are clocked off a first clock and the slave components are clocked off a second clock that is inverted from the first clock. The master-slave counter is a ring counter, and outputs from the master-slave counter are routed to decoding circuitry to generate divided clocks.

Abstract: A simple, but effective method and apparatus for employing the same is utilized to ensure the atomicity of atomic instructions. Two bits which are visible in a register are used. The control bit is read and write accessible. The status bit is read only accessible. The control bit and status bit are coupled such that the state of the status bit is updated with the state of the control bit after a predetermined delay. Therefore, code can be written to utilize the feature to execute an atomic instruction. Execution of the atomic instruction is initiated, the control bit is set and an instruction, such as branch if clear, is executed which causes the processor to wait until the status bit is set before executing subsequent instructions. Therefore, the atomic instruction has sufficient time to complete execution before the status bit is set and subsequent instruction are executed.