Abstract: An immersion cooling server system with AI accelerator apparatuses using in-memory compute chiplet devices. This system includes one or more immersion tanks with heat transfer fluid and configured with at least a condenser device. A plurality of AI accelerator servers is immersed in the heat transfer fluid in a bottom portion of the tanks and is configured to process transformer workloads while cooled by the immersion cooling configuration. Each of the servers includes a plurality of multiprocessors each having at least a first server central processing unit (CPU) and a second server CPU, both of which are coupled to a plurality of switch devices. Each switch device is coupled to a plurality of AI accelerator apparatuses. The apparatus includes one or more chiplets, each of which includes a plurality of digital in-memory compute (DIMC) devices configured to perform high throughput matrix computations for transformer based models.

Abstract: A server system with AI accelerator apparatuses using in-memory compute chiplet devices. The system includes a plurality of multiprocessors each having at least a first server central processing unit (CPU) and a second server CPU, both of which are coupled to a plurality of switch devices. Each switch device is coupled to a plurality of AI accelerator apparatuses. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a CPU, and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions.

Abstract: This disclosure describes multiplexed optical transceivers, such as DWDM multiplexer/demultiplexers, which are aggregated in a server chassis to establish a fabric topology interconnecting blade servers to a dedicated switch module. Blade servers installed in the server chassis can utilize not just Ethernet interfaces to connect to network segments, but also PCIe interfaces as well as a combination of Ethernet and PCIe interfaces. The aggregated optical transceivers multiplex and demultiplex wavelength-specific optical signals using a laser source, reducing power consumption over switched fabric ASICs. Servicing of the multiplexed optical transceivers is facilitated by installation and replacement of a laser source. Scaling and redundancy of fabric topology interconnects can be facilitated by selection of laser sources generating expanded ranges of discrete wavelengths.

Abstract: A composite connector includes modular data connectors, electrical power connectors, a fluid exchange connector, an alignment feature, and a housing. The modular data connectors include electrical data connectors and optical data connectors and are configured to carry data. The electrical power connectors are configured to carry electrical power, and the fluid exchange connector is configured to carry cooling fluid. The composite connector includes an alignment feature to align the composite connector with a complementary connector. The housing of the composite connector is configured to contain the modular data connectors, the electrical power connectors, the fluid exchange connector, and the alignment feature in a confined physical space.

Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

Abstract: In some examples, a printed circuit board assembly can include a printed circuit board having four (4) central processor unit (CPU) sockets disposed thereon and sixty four (64) dual in-line memory modules (DIMMs) disposed thereon. The printed circuit board can have a top surface and a bottom surface with two (2) CPU sockets and thirty two (32) DIMMs disposed on the top surface and two (2) CPU sockets and thirty two (32) DIMMs disposed on the bottom surface.

Abstract: In some examples, a printed circuit board assembly can include a printed circuit board having four (4) central processor unit (CPU) sockets disposed thereon and sixty four (64) dual in-line memory modules (DIMMs) disposed thereon. The printed circuit board can have a top surface and a bottom surface with two (2) CPU sockets and thirty two (32) DIMMs disposed on the top surface and two (2) CPU sockets and thirty two (32) DIMMs disposed on the bottom surface.

Abstract: An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.

Abstract: A network interface controller configured to be hosted by a first server, includes: a first input/output (IO) port configured to be coupled to a network switch; a second IO port configured to be coupled to a corresponding IO port of a second network interface controller of a second server; and a third IO port configured to be coupled to a corresponding IO port of a third network interface controller of a third server.

Abstract: An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.