Patents by Inventor Jayaprakash Naradasi
Jayaprakash Naradasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230288949Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for regulators providing shared current from multiple input supplies. A regulator can include a first portion configured to receive a first supply voltage and to output a first current drawn from the first supply voltage by a load, and a second portion configured to receive a second supply voltage. The regulator can include a current control circuit configured to, responsive to a load current corresponding the load meeting a particular criteria, initiate current sharing such that the load current is subsequently shared between the first supply voltage and the second supply voltage.Type: ApplicationFiled: July 28, 2022Publication date: September 14, 2023Inventors: Ekram H. Bhuiyan, Jayaprakash Naradasi, Srinivasa Rao Sabbineni, Michael Mostovoy
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Patent number: 10129012Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.Type: GrantFiled: March 29, 2017Date of Patent: November 13, 2018Assignee: SanDisk Technologies LLCInventors: Krishnamurthy Dhakshinamurthy, Shajith Musaliar Sirajudeen, Jayaprakash Naradasi, Bhavin Odedara, Yosi Pinto, Rampraveen Somasundaram, Anand Sharma
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Publication number: 20180083764Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.Type: ApplicationFiled: March 29, 2017Publication date: March 22, 2018Applicant: SanDisk Technologies LLCInventors: Krishnamurthy Dhakshinamurthy, Shajith Musaliar Sirajudeen, Jayaprakash Naradasi, Bhavin Odedara, Yosi Pinto, Rampraveen Somasundaram, Anand Sharma
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Patent number: 9660656Abstract: Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.Type: GrantFiled: April 15, 2015Date of Patent: May 23, 2017Assignee: SanDisk Technologies LLCInventors: Ramakrishnan Karungulam Subramanian, Anand Venkitachalam, Jayaprakash Naradasi, Prashant Singhal
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Publication number: 20160308540Abstract: Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.Type: ApplicationFiled: April 15, 2015Publication date: October 20, 2016Inventors: Ramakrishnan Karungulam Subramanian, Anand Venkitachalam, Jayaprakash Naradasi, Prashant Singhal
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Patent number: 9349489Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.Type: GrantFiled: February 20, 2013Date of Patent: May 24, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Sateesh Desireddi, Jayaprakash Naradasi, Anand Venkitachalam, Manuel Antonio D'Abreu, Stephen Skala
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Patent number: 9318215Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to read first data from the non-volatile memory. The first data indicates a first count of storage elements of the group that have a first activation status when sensed with a first reference voltage at a first time. The controller is configured to read second data from the non-volatile memory. The second data indicates a second count of storage elements of the group that have the first activation status when sensed with the first reference voltage at a second time. The controller is configured to generate an updated first reference voltage at least partially based on a difference between the first count and the second count and based on one or more parameters corresponding to a distribution of threshold voltages of storage elements at the first time.Type: GrantFiled: April 11, 2013Date of Patent: April 19, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Sateesh Desireddi, Sachin Krishne Gowda, Jayaprakash Naradasi, Anand Venkitachalam, Manuel Antonio D'Abreu, Stephen Skala
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Patent number: 8874992Abstract: In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction code page count (TEC). The CEC is a page count of error correction code (ECC) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages. In response to the CEC being at least as large as the TEC, the method includes updating a subset of the set of reference voltages conditioned upon a difference between a current mean error count (CMEC) and a previous mean error count being at least as large as a target mean delta error. The CMEC is based on a count of read errors associated with the ECC pages read during the time period.Type: GrantFiled: September 28, 2012Date of Patent: October 28, 2014Assignee: Sandisk Technologies Inc.Inventors: Sateesh Desireddi, Jayaprakash Naradasi, Anand Venkitachalam, Manuel Antonio D'Abreu, Stephen Skala
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Patent number: 8811076Abstract: A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment.Type: GrantFiled: August 30, 2012Date of Patent: August 19, 2014Assignee: SanDisk Technologies Inc.Inventors: Anand Venkitachalam, Sateesh Desireddi, Jayaprakash Naradasi, Manuel Antonio D'Abreu, Stephen Skala
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Publication number: 20140226398Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to read first data from the non-volatile memory. The first data indicates a first count of storage elements of the group that have a first activation status when sensed with a first reference voltage at a first time. The controller is configured to read second data from the non-volatile memory. The second data indicates a second count of storage elements of the group that have the first activation status when sensed with the first reference voltage at a second time. The controller is configured to generate an updated first reference voltage at least partially based on a difference between the first count and the second count and based on one or more parameters corresponding to a distribution of threshold voltages of storage elements at the first time.Type: ApplicationFiled: April 11, 2013Publication date: August 14, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: SATEESH DESIREDDI, SACHIN KRISHNE GOWDA, JAYAPRAKASH NARADASI, ANAND VENKITACHALAM, MANUEL ANTONIO D'ABREU, STEPHEN SKALA
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Publication number: 20140201580Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.Type: ApplicationFiled: February 20, 2013Publication date: July 17, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: SATEESH DESIREDDI, JAYAPRAKASH NARADASI, ANAND VENKITACHALAM, MANUEL ANTONIO D'ABREU, STEPHEN SKALA
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Patent number: 8669817Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: GrantFiled: November 21, 2011Date of Patent: March 11, 2014Assignee: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Publication number: 20140068382Abstract: In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction code page count (TEC). The CEC is a page count of error correction code (ECC) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages. In response to the CEC being at least as large as the TEC, the method includes updating a subset of the set of reference voltages conditioned upon a difference between a current mean error count (CMEC) and a previous mean error count being at least as large as a target mean delta error. The CMEC is based on a count of read errors associated with the ECC pages read during the time period.Type: ApplicationFiled: September 28, 2012Publication date: March 6, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: SATEESH DESIREDDI, JAYAPRAKASH NARADASI, ANAND VENKITACHALAM, MANUEL ANTONIO D'ABREU, STEPHEN SKALA
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Publication number: 20140029336Abstract: A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment.Type: ApplicationFiled: August 30, 2012Publication date: January 30, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: ANAND VENKITACHALAM, SATEESH DESIREDDI, JAYAPRAKASH NARADASI, MANUEL ANTONIO D'ABREU, STEPHEN SKALA
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Patent number: 8605502Abstract: A method includes, in a data storage device that includes a non-volatile memory, reading first data values from memory elements of the non-volatile memory using a set of reference voltages that includes a first reference voltage, and determining a first error count associated with the first reference voltage. The method includes reading second data values from the group of memory elements using a set of modified reference voltages that includes a modified first reference voltage, and determining a modified error count associated with the modified first reference voltage. The method includes updating the set of reference voltages to include the first reference voltage or the modified first reference voltage based on a comparison of the error count to the modified error count.Type: GrantFiled: June 14, 2012Date of Patent: December 10, 2013Assignee: Sandisk Technologies Inc.Inventors: Sateesh Desireddi, Jayaprakash Naradasi, Anand Venkitachalam
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Publication number: 20130314988Abstract: A method includes, in a data storage device that includes a non-volatile memory, reading first data values from memory elements of the non-volatile memory using a set of reference voltages that includes a first reference voltage, and determining a first error count associated with the first reference voltage. The method includes reading second data values from the group of memory elements using a set of modified reference voltages that includes a modified first reference voltage, and determining a modified error count associated with the modified first reference voltage. The method includes updating the set of reference voltages to include the first reference voltage or the modified first reference voltage based on a comparison of the error count to the modified error count.Type: ApplicationFiled: June 14, 2012Publication date: November 28, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: SATEESH DESIREDDI, JAYAPRAKASH NARADASI, ANAND VENKITACHALAM
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Patent number: 8560919Abstract: A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.Type: GrantFiled: February 21, 2011Date of Patent: October 15, 2013Assignee: SanDisk Technologies Inc.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Jayaprakash Naradasi, Anand Venkitachalam
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Patent number: 8392807Abstract: Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation.Type: GrantFiled: September 15, 2010Date of Patent: March 5, 2013Assignee: Sandisk Technologies Inc.Inventors: Jayaprakash Naradasi, Anand Venkitachalam
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Publication number: 20120102379Abstract: A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.Type: ApplicationFiled: February 21, 2011Publication date: April 26, 2012Applicant: SANDISK CORPORATIONInventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, JAYAPRAKASH NARADASI, ANAND VENKITACHALAM
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Publication number: 20120062326Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi