Patents by Inventor JAYASEKHAR THOLIYIL

JAYASEKHAR THOLIYIL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10802903
    Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 13, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sivakumar Radhakrishnan, Malay Trivedi, Jayasekhar Tholiyil, Erik A. McShane, Roger W. Liu, Mahesh S. Natu
  • Patent number: 10496565
    Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Anand K. Enamandram, Sivakumar Radhakrishnan, Jayasekhar Tholiyil, Tina C. Zhong, Malay Trivedi
  • Publication number: 20190042514
    Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.
    Type: Application
    Filed: July 30, 2018
    Publication date: February 7, 2019
    Inventors: Anand K. ENAMANDRAM, Sivakumar RADHAKRISHNAN, Jayasekhar THOLIYIL, Tina C. ZHONG, Malay TRIVEDI
  • Publication number: 20190034264
    Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.
    Type: Application
    Filed: December 18, 2017
    Publication date: January 31, 2019
    Inventors: Sivakumar RADHAKRISHNAN, Malay TRIVEDI, Jayasekhar THOLIYIL, Erik A. MCSHANE, Roger W. LIU, Mahesh S. NATU
  • Patent number: 8868992
    Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Theodore Z. Schoenborn, Philip Abraham, Christopher P. Mozak, David G. Ellis, Jay J. Nejedlo, Bruce Querbach, Zvika Greenfield, Rony Ghattas, Jayasekhar Tholiyil, Charles D. Lucas, Christopher E. Yunker
  • Publication number: 20110161752
    Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: BRYAN L. SPRY, THEODORE Z. SCHOENBORN, PHILIP ABRAHAM, CHRISTOPHER P. MOZAK, DAVID G. ELLIS, JAY J. NEJEDLO, BRUCE QUERBACH, ZVIKA GREENFIELD, RONY GHATTAS, JAYASEKHAR THOLIYIL, CHARLES D. LUCAS, CHRISTOPHER E. YUNKER