Patents by Inventor Jayashankar Bharadwaj

Jayashankar Bharadwaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020035722
    Abstract: In some embodiments, the invention includes a method of compiling instructions of a program. The method includes receiving instructions for code motion and controlling the code motion while interacting with block ordering. The code motion may be done as part of various activities including instruction scheduling, partial redundancy elimination, and loop invariant removal. The scheduling may involve making an assessment of the cost of scheduling an instruction that takes into account generation and/or elimination of branches due to resulting block order update and determining whether to make the code motion based on the cost. Instruction scheduling may involve regeneration of predicate expressions to invert conditional branches.
    Type: Application
    Filed: November 3, 1998
    Publication date: March 21, 2002
    Inventors: CHRISTOPHER M. MCKINSEY, JAYASHANKAR BHARADWAJ
  • Patent number: 5894576
    Abstract: A method is described for scheduling an instruction of a computer program. The instruction is scheduled into an active block of the computer program if no compensation copy is necessary, or if any necessary compensation copy is acceptable.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: April 13, 1999
    Assignee: Intel Corporation
    Inventor: Jayashankar Bharadwaj
  • Patent number: 5787287
    Abstract: A method of representing data dependence and control flow between two instructions in computer-executable instructions. Each instruction is for reading or writing a variable. The sequence of instructions has a plurality of control flow paths. A dependency path vector (DPV) is generated comprising a plurality of bits and representing both the data dependency and the control flow between the first instruction and the second instruction with respect to the variable. One bit of the DPV is allocated for each of the control flow paths in the sequence of instructions, and the value of each bit indicates whether there is a dependency between the first instruction and the second instruction along the corresponding path with respect to the variable.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: July 28, 1998
    Assignee: Intel Corporation
    Inventor: Jayashankar Bharadwaj