Abstract: An image analysis system including at least one processor and at least one memory is provided. The image analysis system is configured to receive image data associated with a brain of a patient, the image data including a first three-dimensional (3D) diffusion weighted imaging (DWI) image acquired using a magnetic resonance imaging (MRI) system and a second 3D DWI image, concurrently provide the first 3D DWI image to a first channel of a trained model and the second 3D DWI image to a second channel of the trained model, receive an indicator associated with the first 3D DWI image and the second 3D DWI image from the model, generate a report based on the indicator, and cause the report to be output to at least one of a memory or a display.

Abstract: Motion artifacts are detected from raw k-space data acquired with a magnetic resonance imaging (“MM”) system. A machine learning model is trained on a training dataset that includes motion-simulated k-space data. The motion-simulated k-space data may be generated by inputting magnetic resonance images to a forward model to convert the images to k-space data while adding motion based on motion parameters. The severity of the simulated motion can be varied, and features of motion artifacts extracted by preprocessing the motion-simulated k-space data. In deployment, the trained machine learning model may be used to detect the presence and/or severity of motion artifacts in k-space data while a subject is being scanned with an MRI scanner.

Abstract: A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit “defect” is intentionally created in the physical layout. Then, the new electrical schematic is extracted from the modified physical layout. Subsequently, if the design “defect” which was created is temporary, the new electrical schematic is simulated, the logical address of the “defect” is determined, and the extracted logical address is compared to the expected address to verify the logical to physical correlation. Alternatively, if the design “defect” which was created is permanent, after the new electrical schematic is extracted from the modified physical layout, the product is fabricated and the known design “defect” location is used to correlate to the electrically-tested defect logical location.

Abstract: Improved methods for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. A first method provides that EMMI is used to identify the physical location of a failing memory bit. A second method provides that a physical location is damaged with a laser, as is used to open hard wired fuses, and then the DUT is electrically tested and the memory built in self test (MEM BIST) repair is used to identify the logical address for the damaged region. A third method provides that a physical location is damaged using an electrical test on the ATE that causes an onboard fuse element in the memory arrays to be broken through the application of a high voltage.

Abstract: A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit “defect” is intentionally created in the physical layout. Then, the new electrical schematic is extracted from the modified physical layout. Subsequently, if the design “defect” which was created is temporary, the new electrical schematic is simulated, the logical address of the “defect” is determined, and the extracted logical address is compared to the expected address to verify the logical to physical correlation. Alternatively, if the design “defect” which was created is permanent, after the new electrical schematic is extracted from the modified physical layout, the product is fabricated and the known design “defect” location is used to correlate to the electrically-tested defect logical location.

Abstract: The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.

Abstract: An apparatus for planarizing a surface of a semiconductor wafer includes a wafer support configured to receive the semiconductor wafer so that the surface of the semiconductor wafer projects from the wafer support. The apparatus also includes a polishing member configured in the form of an endless unitary belt which is devoid of seams. The endless unitary belt is (i) positioned in contact with the surface of the semiconductor wafer and (ii) capable of moving in a linear direction relative to the surface of the semiconductor wafer so as to planarize the surface of the semiconductor wafer. An associated method of linearly planarizing a surface of a semiconductor is also described.

Abstract: A polishing pad surface having a surface designed for chemical mechanical polishing of a substrate surface is described. The polishing pad surface includes a first area on the surface exposed to and capable of contacting a first amount of the substrate surface during chemical-mechanical polishing and a second area on the surface exposed to and capable of contacting a second amount of the substrate surface during chemical-mechanical polishing, wherein the second amount is larger than the first amount of the substrate surface to produce a more uniformly polished substrate surface.

Abstract: A conditioning wafer for conditioning a polishing pad employed in chemical-mechanical polishing of an integrated circuit substrate is described. The conditioning wafer includes a disk having a conditioning surface and a plurality of abrasive particles secured on the conditioning surface of the disk. Furthermore, the abrasive particles engage with the polishing pad when the conditioning wafer contacts the polishing pad during conditioning of the polishing pad.

Abstract: A process of conditioning a polishing pad used in chemical mechanical polishing of an integrated circuit and having a glazed layer is described. The process includes introducing a conditioning reagent including at least one of hydrofluoric acid, buffered oxide etch composition and potassium hydroxide on the polishing pad to dissolve at least a portion of the glazed layer; and abrading the glazed layer and disloding at least some particles from the glazed layer.

Abstract: A post metal chemical-mechanical polishing cleaning process that effectively inhibits corrosion of a metallic plug is described. The process includes providing a partially fabricated integrated circuit (IC) substrate having a metallic plug that is formed by subjecting a metallic surface on the integrated circuit (IC) substrate to chemical-mechanical polishing, which produces a contaminated dielectric layer containing metallic contaminants. The process also includes scrubbing the IC substrate surface in the presence of a mixture including ethylene glycol and hydrofluoric acid to remove at least a portion of the contaminated dielectric layer and to effectively inhibit corrosion of the metallic plug. The mixture has ethylene glycol in an amount that is between about 2 times and about 7 times the amount of hydrofluoric acid.

Abstract: A polishing pad surface designed for chemical mechanical polishing of substrates is described. The polishing pad includes a first area of the surface having formed thereon a first set of grooves and a second area of the surface having formed thereon a second set of grooves, wherein the first set of grooves have a larger cross-sectional area than the second set of grooves.

Abstract: Provided is a chemical mechanical polishing pad having grooves in its polishing surface which have a sub-surface cross-sectional span greater than the grooves' surface opening span. In this way, the edges of the groove are undercut. This provides both increased groove volume for a given pad surface area and groove depth, and variable flexibility in the polishing pad's surface. Grooves in pads of the invention also typically include a neck region at the top of the groove, where the groove side walls are substantially parallel. This provides a margin for the pad to wear during polishing without affecting the pad's surface area. The invention also provides a method and apparatus for cutting grooves in a chemical mechanical polishing pad.

Abstract: Buffered slurries are used in a semiconductor process for chemical mechanical polishing of metal layers, such as aluminum or titanium. The slurries may comprise an oxidant capable of causing a passive oxide film to form on a metal based layer. The oxidant may comprise a diluent and may be optionally formulated with a separate oxidizing agent, such as ammonium peroxydisulfate. The slurries may include a buffer that maintains a slurry pH where the passive metal oxide film is stable. This pH may be between about 4 and about 9.

Abstract: A method for determining the thickness of a film in a film stack using reflectance spectroscopy is provided in which one of the films in the stack has unknown optical constants. Conventional methods of using reflectance measurements to determine the thickness of a film require knowledge of the thicknesses and optical constants of all underlying films. An embodiment involves forming a test layer across a substrate having a known thickness and known optical constants. The thickness of the layer is determined using reflectance measurements. A first layer of the same material is then formed across a second layer at the same conditions that the test layer was formed. Thus, the test layer and the first layer can be assumed to have the same thicknesses. A spectral response curve may be determined for the first layer. The first layer is then processed so that its thickness is no longer known.

Abstract: A substrate holder assembly for immobilizing an integrated circuit (IC) wafer during polishing is described. The substrate holder includes a base plate sized to support the integrated circuit (IC) wafer, a circumferential restraint member arranged with respect to the base plate to engage the IC wafer's edges and a carrier assembly disposed above the base plate and below the IC wafer. The carrier assembly includes a film having a surface that is characterized by a substantially oblate spheroid or hyperboloid surface of rotation, wherein the surface of the film is capable of supporting the IC wafer in a manner causing the IC wafer to bow according to the surface of rotation.