Patents by Inventor Jayashree Kar

Jayashree Kar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to control delay between lanes
    Patent number: 8166215
    Abstract: Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: April 24, 2012
    Assignee: Intel Corporation
    Inventors: Srikrishnan Venkataraman, Jayashree Kar, Sudarshan D. Solanki, Priyavadan Ramdas Patel, Michael M. DeSmith, David G. Figueroa
  • Noise reduction method by implementing certain port-to-port delay
    Patent number: 7975158
    Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Muhammed Elgousi, Jayashree Kar, David G. Figueroa, Srikrishnan Venkataraman
  • NOISE REDUCTION METHOD BY IMPLEMENTING CERTAIN PORT-TO-PORT DELAY
    Publication number: 20090259787
    Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 31, 2007
    Publication date: October 15, 2009
    Inventors: Muhammed Elgousi, Jayashree Kar, David G. Figueroa, Srikrishnan Venkataraman
  • Power plane to reduce voltage difference between connector power pins
    Patent number: 7492605
    Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, Jayashree Kar, David G. Figueroa, Dong Zhong
  • Power plane to reduce voltage difference between connector power pins
    Publication number: 20070295818
    Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 27, 2007
    Inventors: Yuan-Liang Li, Jayashree Kar, David G. Figueroa, Dong Zhong
  • Method to control delay between lanes
    Publication number: 20070150197
    Abstract: Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Srikrishnan Venkataraman, Jayashree Kar, Sudarshan Solanki, P. Patel, Michael DeSmith, David Figueroa