Patents by Inventor Jayashree Saxena
Jayashree Saxena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10107859Abstract: An example method for determining test conditions for at-speed transition delay fault tests on semiconductor devices is provided and includes analyzing scan patterns for testing a circuit of a device-under-test (DUT), identifying paths in the circuit activated by the scan patterns, determining behavior of the paths at different test corners, generating a histogram for each scan pattern representing a distribution of paths exhibiting worst-case behavior at corresponding test corners, generating an ordered set of scan pattern-test corner combinations based on the histogram, selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, generating an ordered test set including the ordered scan pattern-test corner combinations with the selected threshold, and feeding the ordered test set to a test instrument, the test instrument testing the DUT according to the ordered test set, the tests being performed at the test corners listed above the selected threshold.Type: GrantFiled: March 30, 2016Date of Patent: October 23, 2018Assignee: Anora LLCInventors: Jayashree Saxena, Jeremy Lee, Pramodchandran Variyam
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Patent number: 9103882Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: May 16, 2014Date of Patent: August 11, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayashree Saxena, Lee D. Whetsel
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Publication number: 20140250342Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: ApplicationFiled: May 16, 2014Publication date: September 4, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 8769358Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: August 16, 2013Date of Patent: July 1, 2014Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Publication number: 20130339773Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: ApplicationFiled: August 16, 2013Publication date: December 19, 2013Applicant: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 8539294Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: October 22, 2012Date of Patent: September 17, 2013Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 8321729Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: April 21, 2011Date of Patent: November 27, 2012Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Publication number: 20110197102Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: ApplicationFiled: April 21, 2011Publication date: August 11, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 7954030Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: December 7, 2010Date of Patent: May 31, 2011Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Publication number: 20110078524Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 7870451Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: July 30, 2009Date of Patent: January 11, 2011Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 7865849Abstract: A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.Type: GrantFiled: February 15, 2008Date of Patent: January 4, 2011Assignee: Texas Instruments IncorporatedInventors: Kenneth M. Butler, John M. Carulli, Jr., Jayashree Saxena, Amit P. Vasavada
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Publication number: 20100023823Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: ApplicationFiled: July 30, 2009Publication date: January 28, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 7617429Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: March 9, 2007Date of Patent: November 10, 2009Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel
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Patent number: 7580807Abstract: Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test. The MMS interface includes a test protocol manager that may receive test stimulus and send the test stimulus to cores of the device under test. The test protocol manager may receive test responses from cores of the device under test and generate test comparisons based on comparisons between the test responses and expected responses. The test protocol manager may store the test comparisons on the device under test and communicate the stored test comparisons to automated test equipment (ATE) upon being queried by the ATE. The device under test may send the test comparisons to the ATE over a low-bandwidth communication.Type: GrantFiled: June 12, 2007Date of Patent: August 25, 2009Assignee: Texas Instruments IncorporatedInventors: Matthew Craig Bullock, Alessandro Paglieri, Jayashree Saxena
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Publication number: 20090210830Abstract: A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Applicant: Texas Instruments IncorporatedInventors: Kenneth M. Butler, John M. Carulli, JR., Jayashree Saxena, Amit P. Vasavada
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Patent number: 7324914Abstract: A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.Type: GrantFiled: October 29, 2004Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Atul K. Jain, Venugopal Puvvada, Jayashree Saxena
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Publication number: 20080015798Abstract: Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test. The MMS interface includes a test protocol manager that may receive test stimulus and send the test stimulus to cores of the device under test. The test protocol manager may receive test responses from cores of the device under test and generate test comparisons based on comparisons between the test responses and expected responses. The test protocol manager may store the test comparisons on the device under test and communicate the stored test comparisons to automated test equipment (ATE) upon being queried by the ATE. The device under test may send the test comparisons to the ATE over a low-bandwidth communication.Type: ApplicationFiled: June 12, 2007Publication date: January 17, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew Bullock, Alessandro Paglieri, Jayashree Saxena
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Publication number: 20070162805Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: ApplicationFiled: March 9, 2007Publication date: July 12, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayashree Saxena, Lee Whetsel
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Patent number: 7219284Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.Type: GrantFiled: July 6, 2004Date of Patent: May 15, 2007Assignee: Texas Instruments IncorporatedInventors: Jayashree Saxena, Lee D. Whetsel