Patents by Inventor Jayasimha Prasad
Jayasimha Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10147801Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.Type: GrantFiled: August 10, 2012Date of Patent: December 4, 2018Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 9159804Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: GrantFiled: September 16, 2014Date of Patent: October 13, 2015Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8969158Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: GrantFiled: January 28, 2014Date of Patent: March 3, 2015Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20140374826Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: ApplicationFiled: September 16, 2014Publication date: December 25, 2014Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8866217Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: GrantFiled: August 10, 2012Date of Patent: October 21, 2014Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20140147979Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: ApplicationFiled: January 28, 2014Publication date: May 29, 2014Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8709899Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.Type: GrantFiled: August 10, 2012Date of Patent: April 29, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
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Patent number: 8647950Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: GrantFiled: August 10, 2012Date of Patent: February 11, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130115744Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: ApplicationFiled: August 10, 2012Publication date: May 9, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130109143Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
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Publication number: 20130105888Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130105887Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan