Patents by Inventor Jaydeep Kulkarni

Jaydeep Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11881435
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 23, 2024
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Publication number: 20240005982
    Abstract: A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes first, second, and third sets of a plurality of transistor devices. The first set is configured to form at least one write port. The at least one write port receives digital data. The second set of the plurality of transistor devices is configured as an inverter pair that stores the digital data. The third set of the plurality of transistor devices is configured to form at least one read port. The at least one read port is used to access the digital data from the inverter pair and output the digital data on the local bitline. The plurality of transistor devices consists of an equal number of P-channel transistor devices and N-channel transistor devices.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Amlan Ghosh, John R. Riley, Feroze Merchant, Jaydeep Kulkarni
  • Publication number: 20230419010
    Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
    Type: Application
    Filed: December 14, 2022
    Publication date: December 28, 2023
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Jaydeep Kulkarni
  • Publication number: 20230124676
    Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Jaydeep Kulkarni
  • Publication number: 20230118578
    Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Jaydeep Kulkarni
  • Publication number: 20230116581
    Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
  • Patent number: 11600525
    Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 7, 2023
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
  • Patent number: 11489526
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Publication number: 20220270930
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 25, 2022
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Patent number: 11355397
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 7, 2022
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Publication number: 20210366771
    Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
    Type: Application
    Filed: December 21, 2018
    Publication date: November 25, 2021
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
  • Publication number: 20210350061
    Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
    Type: Application
    Filed: September 6, 2019
    Publication date: November 11, 2021
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Jaydeep Kulkarni
  • Publication number: 20200365464
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Publication number: 20200358443
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Patent number: 10713333
    Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Farhana Sheikh, Ankit Sharma, Jaydeep Kulkarni
  • Patent number: 10666259
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Patent number: 10511224
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 10217495
    Abstract: Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventor: Jaydeep Kulkarni
  • Patent number: 10199091
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Minki Cho, Jaydeep Kulkarni, Carlos Tokunaga, Muhammad Khellah, James Tschanz
  • Publication number: 20180336161
    Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 22, 2018
    Inventors: Farhana SHEIKH, Ankit SHARMA, Jaydeep KULKARNI