Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

Abstract: Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.

Abstract: Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.

Abstract: Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.

Abstract: Methods and systems for detection of selected defects in relatively noisy inspection data are provided. One method includes applying a spatial filter algorithm to inspection data acquired across an area on a substrate to determine a first portion of the inspection data that has a higher probability of being a selected type of defect than a second portion of the inspection data. The selected type of defect includes a non-point defect. The inspection data is generated by combining two or more raw inspection data corresponding to substantially the same locations on the substrate. The method also includes generating a two-dimensional map illustrating the first portion of the inspection data. The method further includes searching the two-dimensional map for an event that has spatial characteristics that approximately match spatial characteristics of the selected type of defect and determining if the event corresponds to a defect having the selected type.

Abstract: Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.

Abstract: Systems and methods for providing micro defect inspection capabilities for optical systems are disclosed. Each given wafer image is filtered, treated and normalized prior to performing surface feature detection and quantification. A partitioning scheme is utilized to partition the wafer image into a plurality of measurement sites and metric values are calculated for each of the plurality of measurement sites. Furthermore, transformation steps may also be utilized to extract additional process relevant metric values for analysis purposes.

Abstract: Predictive modeling based focus error prediction method and system are disclosed. The method includes obtaining wafer geometry measurements of a plurality of training wafers and grouping the plurality of training wafers to provide at least one training group based on relative homogeneity of wafer geometry measurements among the plurality of training wafers. For each particular training group of the at least one training group, a predictive model is develop utilizing non-linear predictive modeling. The predictive model establishes correlations between wafer geometry parameters and focus error measurements obtained for each wafer within that particular training group, and the predictive model can be utilized to provide focus error prediction for an incoming wafer belonging to that particular training group.

Abstract: Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.

Abstract: Systems and methods for providing improved scanner corrections are disclosed. Scanner corrections provided in accordance with the present disclosure may be referred to as wafer geometry aware scanner corrections. More specifically, wafer geometry and/or wafer shape signature information are utilized to improve scanner corrections. By removing the wafer geometry as one of the error sources that may affect the overlay accuracy, better scanner corrections can be obtained because one less contributing factor needs to be modeled.

Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.

Abstract: A method of providing high accuracy inspection or metrology in a bright-field differential interference contrast (BF-DIC) system is described. This method can include creating first and second beams from a first light beam. The first and second beams have round cross-sections, and form first partially overlapping scanning spots radially displaced on a substrate. Third and fourth beams are created from the first light beam or a second light beam. The third and fourth beams have elliptical cross-sections, and form second partially overlapping scanning spots tangentially displaced on the substrate. At least one portion of the substrate can be scanned using the first and second partially overlapping scanning spots as the substrate is rotated. Radial and tangential slopes can be determined using measurements obtained from the scanning using the first and second partially overlapping scanning spots. These slopes can be used to determine wafer shape or any localized topography feature.

Abstract: Systems and methods for providing improved scanner corrections are disclosed. Scanner corrections provided in accordance with the present disclosure may be referred to as wafer geometry aware scanner corrections. More specifically, wafer geometry and/or wafer shape signature information are utilized to improve scanner corrections. By removing the wafer geometry as one of the error sources that may affect the overlay accuracy, better scanner corrections can be obtained because one less contributing factor needs to be modeled.

Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.

Abstract: Systems and methods for providing improved scanner corrections are disclosed. Scanner corrections provided in accordance with the present disclosure may be referred to as wafer geometry aware scanner corrections. More specifically, wafer geometry and/or wafer shape signature information are utilized to improve scanner corrections. By removing the wafer geometry as one of the error sources that may affect the overlay accuracy, better scanner corrections can be obtained because one less contributing factor needs to be modeled.

Abstract: A method of providing high accuracy inspection or metrology in a bright-field differential interference contrast (BF-DIC) system is described. This method can include creating first and second beams from a first light beam. The first and second beams have round cross-sections, and form first partially overlapping scanning spots radially displaced on a substrate. Third and fourth beams are created from the first light beam or a second light beam. The third and fourth beams have elliptical cross-sections, and form second partially overlapping scanning spots tangentially displaced on the substrate. At least one portion of the substrate can be scanned using the first and second partially overlapping scanning spots as the substrate is rotated. Radial and tangential slopes can be determined using measurements obtained from the scanning using the first and second partially overlapping scanning spots. These slopes can be used to determine wafer shape or any localized topography feature.

Abstract: A method and system for modeling and analyzing wafer nanotopography data utilizes a nonlinear contact finite element model. Inputs to the model include lithography chuck parameters and site-based geometry data. Outputs from the model include in-plane distortions and out-of-plane distortions, from which defocus and overlay can be derived.

Abstract: A method for enabling more accurate measurements of localized features on wafers is disclosed. The method includes: a) performing high order surface fitting to more effectively remove the low frequency shape components and also to reduce possible signal attenuations commonly observed from SEMI standard high pass, such as Gaussian and Double Gaussian filtering; b) constructing and applying a proper two dimensional LFM window to the residual image from the surface fitting processing stage to effectively reduce the residual artifacts at the region boundaries; c) calculating the metrics of the region using the artifact-reduced image to obtain more accurate and reliable measurements; and d) using site-based metrics obtained from front and back surface data to quantify the features of interest. Additional steps may also include: filtering data from measurements of localized features on wafers and adjusting the filtering behavior according to the statistics of extreme data samples.

Abstract: Disclosed herein is a method to enhance detection and quantification of features in the wafer edge/wafer roll off regions. Modifications and improvements have been made to earlier methods which enable improved accuracy and increased scope of feature detection.