Patents by Inventor Jaydip Bharatkumar Patel

Jaydip Bharatkumar Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12062410
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Publication number: 20220180905
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Publication number: 20210407582
    Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Jaydip Bharatkumar Patel, Everardo Flores, III, Khaled Hasnat, Max F. Hineman
  • Patent number: 11195575
    Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Jaydip Bharatkumar Patel, Everardo Flores, III, Khaled Hasnat, Max F. Hineman