Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench.

Abstract: Methods, apparatuses, and systems related to conductive structures are described. An example conductive structure includes a first conductive material including a conductive metal nitride, where the first conductive material has a thickness of at least 0.5 nanometers, and a second conductive material including a conductive metal, where the second conductive material is disposed on a first surface of the first conductive material.

Abstract: A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a recess formed in a semiconductor material; a dielectric structure formed in the recess; and a control gate for a transistor of a memory cell, the control gate including a first conductive portion formed in the recess and separated from the semiconductor material by a first portion of the dielectric structure, the first dielectric portion including a first dielectric material between the semiconductor material and the second dielectric material, and a second dielectric material between the first dielectric material and the first conductive portion; and the control gate including the second conductive portion formed over the first conductive portion and separated from the semiconductor material by a second portion of the dielectric structure between the semiconductor material and second conductive portion.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator extends along sidewalls and around a bottom of the conductive gate between the conductive gate and the semiconductor material. A pair of source/drain regions are in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region in the semiconductor material below the pair of source/drain regions extends along sidewalls and around a bottom of the trench. The gate insulator comprises a low-k material and a high-k material. The low-k material is characterized by its dielectric constant k being no greater than 4.0. The high-k material is both (a) and (b), where: (a): characterized by its dielectric constant k being greater than 4.0; and (b): comprising SixMyO, where “M” is one or more of Al, metal(s) from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table; “x” is 0.999 to 0.6; and “y” is 0.001 to 0.

Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.