Abstract: To program MRAM memory cells current must flow from the memory cell's corresponding bit line to its corresponding word line or from the word line to bit line. To accomplish this, the bit line and word line decoders must be capable of sourcing current (when driving a line positive) and sinking current (when pulling the line negative) to account the memory cell's bipolar nature. Consequently, the decoders must be bipolar. For the negative select switches NMOS devices are used and for the positive select switches PMOS switches are used. To reduce layout area and routing, the negative select switches and positive select switches are separately grouped, with a subset of the positive select switches located between subsets of the negative select switches and vice-versa. The connection for the decoder switches are routed to a central hook-up region for connection to the control lines of the cross-point array.

Abstract: For MRAM and other memory cell technologies that use threshold selector switches such as ovonic threshold switches, when accessing a selected memory cell, such as for a read, the voltage across the memory cell needs to be sufficient to turn on the threshold selector switch. This results in a current spike that can damage the memory cell and disturb a data value written in it. To reduce such spikes, the local select switches biasing to the selected word line and selected bit line can be biased to limit the current flow from the decoding circuitry when the threshold selector switch turns on.

Abstract: An apparatus includes a memory cell including a magnetic memory element coupled in series with a selector element, the memory cell including a first terminal coupled to a word line driver circuit and a second terminal coupled to a bit line driver circuit, and an amplifier circuit comprising an input terminal coupled to the bit line driver circuit, and an output terminal coupled to a current source configured to conduct a read current. The amplifier circuit is configured to amplify a voltage that is based on a difference between a first voltage across the memory cell and a second voltage across the memory cell.

Abstract: To program MRAM memory cells current must flow from the memory cell's corresponding bit line to its corresponding word line or from the word line to bit line. To accomplish this, the bit line and word line decoders must be capable of sourcing current (when driving a line positive) and sinking current (when pulling the line negative) to account the memory cell's bipolar nature. Consequently, the decoders must be bipolar. For the negative select switches NMOS devices are used and for the positive select switches PMOS switches are used. To reduce layout area and routing, the negative select switches and positive select switches are separately grouped, with a subset of the positive select switches located between subsets of the negative select switches and vice-versa. The connection for the decoder switches are routed to a central hook-up region for connection to the control lines of the cross-point array.

Abstract: An apparatus includes one or more control circuits to connect to a multi-story memory structure. The multi-story memory structure includes nonvolatile memory cells each having a programmable resistive element. The control circuits are configured to receive addresses of selected cells and for each selected cell determine a story in which the selected cell is located from stories including a first story between a first word line layer and a bit line layer and a second story between the bit line layer and a second word line layer. The control circuits are further configured to connect a sense amplifier to a first selected nonvolatile memory cell in the first story through a bit line of the bit line layer and connect the sense amplifier to a second selected nonvolatile memory cell in the second story through a second word line of the second word line layer.

Abstract: A non-volatile memory includes a memory array including non-volatile memory cells and a first decoder module coupled to the memory array. The first decoder module includes word line decoders coupled to the non-volatile memory cells, bit line decoders coupled to the non-volatile memory cells, a first cluster including a first set of the word line decoders and the bit line decoders, a second cluster including a second set of the word line decoders and the bit line decoders, and a region surrounding and separating the first cluster and the second cluster. The first set of the word line decoders and the bit line decoders abut one another and the second set of the word line decoders and the bit line decoders abut one another.

Abstract: A non-volatile memory includes a memory array having a plurality of non-volatile memory cells, and a first decoder module coupled to the memory array. The first decoder module includes a first plurality of word line decoders coupled to the non-volatile memory cells, a first plurality of bit line decoders coupled to the non-volatile memory cells, a first multiplexor circuit configured to selectively couple one of the first plurality of word line decoders or one of the first plurality of bit line decoders to a positive bias node, and a second multiplexor circuit configured to selectively couple one of the first plurality of word line decoders or one of the first plurality of bit line decoders to a negative bias node. The first multiplexor circuit and the second multiplexor circuit are each coupled to a word line decoder and a bit line decoder outside a boundary of the first decoder module.

Abstract: An apparatus includes one or more control circuit configured to connect to a nonvolatile memory cell structure that includes nonvolatile memory cells each having a programmable resistive element. The one or more control circuit is configured to receive an address that corresponds to a location in the nonvolatile memory cell structure and set a variable resistor according to the location. The variable resistor is connected in series with a selected nonvolatile memory cell that is located at the location. The one or more control circuit is further configured to drive a memory access current through the selected nonvolatile memory cell and the variable resistor in series.