Patents by Inventor Jaydutt Jagdish Joshi

Jaydutt Jagdish Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141901
    Abstract: Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: November 27, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guohao Zhang, Hardik Bhupendra Modi, Jaydutt Jagdish Joshi, Bhuvaneshwaran Vijayakumar, Dinhphuoc Vu Hoang
  • Publication number: 20180198436
    Abstract: According to some implementations, a radio-frequency (RF) module is disclosed, comprising a first substrate. The radio-frequency module also includes a radio-frequency device mounted on the first substrate, the radio-frequency device including a second substrate. In some embodiments, the second substrate includes a first side and a second side, a set of support structures implemented on the second side of the substrate, the set of support structures defining a mounting volume on the second side of the second substrate, and a component implemented within the mounting volume. The radio-frequency module may further comprise a first overmold structure encapsulating at least a portion of the set of support structures.
    Type: Application
    Filed: December 7, 2017
    Publication date: July 12, 2018
    Inventor: Jaydutt Jagdish JOSHI
  • Patent number: 9691683
    Abstract: Methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 27, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Jaydutt Jagdish Joshi
  • Publication number: 20160380603
    Abstract: Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Inventors: Guohao Zhang, Hardik Bhupendra Modi, Jaydutt Jagdish Joshi, Bhuvaneshwaran Vijayakumar, Dinhphuoc Vu Hoang
  • Patent number: 9467940
    Abstract: Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 11, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guohao Zhang, Hardik Bhupendra Modi, Jaydutt Jagdish Joshi, Bhuvaneshwaran Vijayakumar, Dinhphuoc Vu Hoang
  • Patent number: 9401316
    Abstract: Electronic devices with improved thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: July 26, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventor: Jaydutt Jagdish Joshi
  • Publication number: 20150243580
    Abstract: Methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 27, 2015
    Inventor: Jaydutt Jagdish Joshi
  • Publication number: 20150243579
    Abstract: Electronic devices with improved thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 27, 2015
    Inventor: Jaydutt Jagdish Joshi