Abstract: Chemical vapor deposition (CVD) is enhanced by compensating for a depleted gas concentration zone in a CVD reactor. According to an example embodiment of the present invention, a chemical-vapor deposition (CVD) gas injector is adapted to supply gas to a CVD chamber in a manner that enhances the properties of deposited films. The injector has a gas inlet coupled to a gas source and supplies gas from the source to the CVD system via at least one gas outlet. The injector is adapted to deliver gas in a manner that sufficiently maintains uniform supply of the gas in a zone of the CVD system that would exhibit a depleted gas supply absent the injector. The uniform gas supply improves the CVD process in various manners, including making possible the deposition of films having uniform properties, such as reflectivity, extinction coefficient, thickness and refractive index.

Abstract: A film stack for forming shallow trench isolation among transistors and other devices on a semiconductor substrate is provided, including a plurality of light absorbing layers alternating between a layer of SiON and a layer of SiO2 and having a combined extinction coefficient >0.5. As reflected light interacts with the light absorbing layers, a substantial amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches may be formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer.

Abstract: A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved throughput of a BARC layer furnace deposition device. This improvement is achieved by providing for a higher flow rate of NH3 during the BARC deposition process. Also, this improvement may be achieved by reducing the temperature gradient of the BARC layer furnace deposition device to approximately 715-750° C. For example, approximately a 1-10% blend of NH3 in at least one of Argon, Nitrogen, and Helium is utilized. By diluting the NH3, a higher flow rate may be utilized in the furnace deposition device, thus allowing for an increased load uniformity of the BARC layer thickness, refractive index, extinction coefficient, and reflectivity characteristics. Also, the NH3 depletion is reduced and preferably eliminated due to the higher flow rate of the diluted NH3.

Abstract: Critical dimension variation of photolithographically formed features on a semiconductor substrate is reduced by measuring the reflectivity of a photoresist layer and an underlying layer, such as a polysilicon layer, and adjusting the exposure level of the photoresist in accordance with the measured reflectivity. This allows precise control of feature width on the photoresist, which in turn allows precision etching of the underlying layer to accurately form a feature, such as a gate electrode.

Abstract: Polysilicon gates are formed with greater accuracy and consistency by depositing a silicon carbide antireflective layer on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon carbide layer in the same tool.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an antireflective layer, of silicon oxime, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the silicon oxime layer in the same tool.

Abstract: Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in the same tool.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

Abstract: To attenuate a CMP polishing rate differential which tends to occur over the surface of a semiconductor substrate surface which has had one or more layers formed thereon, surface characteristics of the upper surface which are representative of the thickness, for example, of a layer which is being removed either in part or in its entirety, are monitored and surface profile information is developed using a suitable algorithm and used to control the timing with which force is applied by one or more of a plurality of actuators disposed on the other side of the wafer, in a manner wherein areas which have undergone more removal than others, are forced into contact with the polishing pad with a force which is reduced as compared that which is applied to localized high areas wherein a lesser amount of the layer has been removed.

Abstract: Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in the same tool.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photolithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer, e.g., amorphous silicon, on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the amorphous silicon layer in the same tool.