Abstract: An apparatus having a plurality of first circuits, a second circuit and a plurality of processor circuits is disclosed. Each first circuit is configured to store a plurality of samples corresponding to a plurality of channels. At least two of the samples having different widths. The second circuit is configured to store a plurality of frames each sized to contain two or more of the samples. The processor circuits are configured to (i) read the samples from the first circuits respectively, (ii) generate a transmit one of the frames by writing the samples to the second circuit based on one or more access pointers and (iii) pass control of the access pointers among the processor circuits.