Abstract: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.

Abstract: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.

Abstract: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.

Abstract: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.

Abstract: A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.

Abstract: A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.