Abstract: In one embodiment, an apparatus includes: a plurality of execution circuits to execute and instruct micro-operations (?ops), where a subset of the plurality of execution circuits are capable of execution of a fused ?op; a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse at least some pairs of producer-consumer ?ops into fused ?ops; and a fusion throttle circuit coupled to the fusion circuit, wherein the fusion throttle circuit is to prevent a first ?op from being fused with another ?op based at least in part on historical information associated with the first ?op. Other embodiments are described and claimed.

Abstract: An apparatus and method for eliminating load instruction execution. For example, one embodiment includes: circuitry to track execution of a plurality of load instructions and responsively update tracking tables; allocation circuitry to allocate a first source register to an instance of the first load instruction and to identify locations of the corresponding data elements in the cache line based on the tracking tables; execution circuitry to load data corresponding to the instance of the first load instruction from the cache line and to load the data elements corresponding to instances of the subsequent load instructions to the same source register; the allocation circuitry to indicate the first source register to the instances of the subsequent load instructions and respective locations of the data elements in the first source register, the instances of the subsequent load instructions to move the respective data elements from the first source register to destination registers.

Abstract: An apparatus and method for improving the efficiency of sequences of load instructions. For example, one embodiment of a method comprises: storing, in one or more tracking structures of a memory operations circuit, information related to executed instances of a load instruction, including a loaded data value, a physical address from which the loaded data value was accessed, and a flag to be set to a first value when new instances of the load instruction are to be excluded from execution; detecting a first instance of the load instruction when the flag is set to the first value; and responsively replacing the first instance of the load instruction with a move instruction which, when executed, is to move the loaded data value from a first register to a destination architectural register indicated by the new load instruction.

Abstract: Techniques and mechanisms for a processor to determine an execution of instructions based on a prediction of a taken branch. In an embodiment, a first prediction unit generates each of multiple branch predictions in one cycle of successive branch prediction cycles. An indication of the branch predictions is provided to an execution pipeline, which prepares to execute an instruction based on the indication. Where a first one of the branch predictions is determined to be of a low confidence type, said first branch prediction is further indicated to a second prediction unit, which performs a second branch prediction based on the same branch instruction for which the first branch prediction was made. In another embodiment, the second prediction unit signals that a state of the execution pipeline is to be cleared, based on a determination that the first and second branch predictions are inconsistent with each other.

Abstract: Techniques for bandwidth aware simultaneous multithreading are described. In an embodiment, an apparatus includes front-end circuitry and back-end circuitry. The front-end circuitry is to process at least two instruction threads in a plurality of front-end pipeline stages. The front-end circuitry is to operate in a first mode and a second mode. In the first mode at least one of the plurality of front-end pipeline stages is configured to process only one of the at least two instruction threads per clock cycle. in the second mode the at least one of the plurality of front-end pipeline stages is configured to process at least two of the at least two instruction threads per clock cycle. The back-end circuitry is to execute operations based on the at least two instruction threads.

Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, and wherein each of the first processor core and the second processor core is to record a respective list of registers modified during execution of their respective instruction segments.

Abstract: Techniques for register renaming caching are described. In an embodiment, an apparatus includes a register renaming cache, front-end circuitry, lookup circuitry, and execution circuitry. The register renaming cache is to store register renaming information associated with an instruction trace. The register renaming information is to be learned from a first execution of the instruction trace and is to be used to perform register renaming in connection with a second execution of the instruction trace. The front-end circuitry is to provide, based on the instruction trace, operations for execution. The lookup circuitry to look in the register renaming cache for entries corresponding to the operations. The execution circuitry is to execute the instruction trace.

Abstract: Techniques for software defined super core usage are described. In some examples, in a super core usage each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, wherein the single virtual core is to support at least one of performance throttling or power throttling.

Abstract: Techniques for software defined super core usage are described. In some examples, a first and second processor core are to operate as a single virtual core enabled by the operating system to fetch the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using flow control instructions that have been inserted into the single threaded program.

Abstract: Techniques for usage of software defined super cores are described. In some examples, in a super core includes a first processor core to execute a first set of instruction segments of the single threaded program, wherein the first processor core is to include a disambiguation predictor for a second processor core to predict a disambiguation of a load for the first processor core against older stores of the second processor core.

Abstract: Techniques for software defined super core usage are described. In some examples, in a super core each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by an operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.

Abstract: Techniques for software defined super core usage are described. In some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.

Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, wherein each of the first and second processor cores is to include a shadow store buffer to track store addresses of the other core.

Abstract: Techniques for early resteering of a branch misprediction are described. Examples detailed herein use a virtual run-ahead mechanism in the core. On a branch misprediction for an hard-to-predict (H2P) branch, a subset of the backslice of the H2P branch are replayed from the out-of-order engine directly (while the main thread is flushing and restarting execution from the front-end).

Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space, wherein the instruction segments are to include one or more of a store instruction to store live register data to be shared with another core and a load instruction to load live register data shared by another core.

Abstract: An apparatus and method for efficient loop streaming operation on a processor. For example, one embodiment of a processor comprises: a memory controller to couple to a memory; an interconnect coupled to the memory controller; a plurality of cores coupled to the interconnect, a core of the plurality of cores comprising: fetch circuitry to fetch a plurality of instructions from the memory; a decoder to decode the plurality of instructions to generate a plurality of micro-operations associated with a loop construct and to extract a hint from at least one of the plurality of instructions indicating execution characteristics of the loop construct; a scheduler to schedule a first iteration of the plurality of micro-operations for execution by execution circuitry; and a loop stream detector to detect the loop construct and to cause the scheduler to schedule at least a second iteration of the plurality of micro-operations for execution by the execution circuitry in accordance with the hint.

Abstract: Techniques for software defined super cores are described.

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space, wherein the instruction segments are to include one or more of a store instruction to store live register data to be shared with another core and a load instruction to load live register data shared by another core.

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.