Patents by Inventor Jayesh Gaur

Jayesh Gaur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250217288
    Abstract: Techniques for register renaming caching are described. In an embodiment, an apparatus includes a register renaming cache, front-end circuitry, lookup circuitry, and execution circuitry. The register renaming cache is to store register renaming information associated with an instruction trace. The register renaming information is to be learned from a first execution of the instruction trace and is to be used to perform register renaming in connection with a second execution of the instruction trace. The front-end circuitry is to provide, based on the instruction trace, operations for execution. The lookup circuitry to look in the register renaming cache for entries corresponding to the operations. The execution circuitry is to execute the instruction trace.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Adithya Ranganathan, Jayesh Gaur, Regev Shemy, Sreenivas Subramoney
  • Publication number: 20250217146
    Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, and wherein each of the first processor core and the second processor core is to record a respective list of registers modified during execution of their respective instruction segments.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte
  • Publication number: 20250217154
    Abstract: Techniques for software defined super core usage are described. In some examples, in a super core usage each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, wherein the single virtual core is to support at least one of performance throttling or power throttling.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte
  • Publication number: 20250217157
    Abstract: Techniques for software defined super core usage are described. In some examples, a first and second processor core are to operate as a single virtual core enabled by the operating system to fetch the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using flow control instructions that have been inserted into the single threaded program.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte, Ariel Sabba, Ori Lempel, Lihu Rappoport, Sreenivas Subramoney
  • Publication number: 20250217158
    Abstract: Techniques for usage of software defined super cores are described. In some examples, in a super core includes a first processor core to execute a first set of instruction segments of the single threaded program, wherein the first processor core is to include a disambiguation predictor for a second processor core to predict a disambiguation of a load for the first processor core against older stores of the second processor core.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte, Stanislav Shwartsman
  • Publication number: 20250217144
    Abstract: Techniques for software defined super core usage are described. In some examples, in a super core each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by an operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte
  • Publication number: 20250217160
    Abstract: Techniques for software defined super core usage are described. In some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte, Sreenivas Subramoney
  • Publication number: 20250217143
    Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, wherein each of the first and second processor cores is to include a shadow store buffer to track store addresses of the other core.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte, Anant Nori, Sudhanshu Shukla
  • Publication number: 20250217155
    Abstract: Techniques for early resteering of a branch misprediction are described. Examples detailed herein use a virtual run-ahead mechanism in the core. On a branch misprediction for an hard-to-predict (H2P) branch, a subset of the backslice of the H2P branch are replayed from the out-of-order engine directly (while the main thread is flushing and restarting execution from the front-end).
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Aniket Deshmukh, Sufiyan Syed, Jayesh Gaur, Sreenivas Subramoney
  • Publication number: 20250217211
    Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space, wherein the instruction segments are to include one or more of a store instruction to store live register data to be shared with another core and a load instruction to load live register data shared by another core.
    Type: Application
    Filed: December 30, 2023
    Publication date: July 3, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte, Anant Nori, Sreenivas Subramoney
  • Publication number: 20250199813
    Abstract: An apparatus and method for efficient loop streaming operation on a processor. For example, one embodiment of a processor comprises: a memory controller to couple to a memory; an interconnect coupled to the memory controller; a plurality of cores coupled to the interconnect, a core of the plurality of cores comprising: fetch circuitry to fetch a plurality of instructions from the memory; a decoder to decode the plurality of instructions to generate a plurality of micro-operations associated with a loop construct and to extract a hint from at least one of the plurality of instructions indicating execution characteristics of the loop construct; a scheduler to schedule a first iteration of the plurality of micro-operations for execution by execution circuitry; and a loop stream detector to detect the loop construct and to cause the scheduler to schedule at least a second iteration of the plurality of micro-operations for execution by the execution circuitry in accordance with the hint.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 19, 2025
    Inventors: Sumeet BANDISHTE, Sudhanshu SHUKLA, Jayesh GAUR
  • Publication number: 20250165255
    Abstract: Techniques for software defined super cores are described.
    Type: Application
    Filed: June 28, 2024
    Publication date: May 22, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte
  • Publication number: 20250117329
    Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 14, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Jayesh Gaur, Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi Feghali
  • Publication number: 20250004766
    Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space, wherein the instruction segments are to include one or more of a store instruction to store live register data to be shared with another core and a load instruction to load live register data shared by another core.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 2, 2025
    Inventors: Jayesh Gaur, Sumeet Bandishte, Anant Nori, Michael Chynoweth, Sreenivas Subramoney, Adi Yoaz, Anshuman Dhuliya
  • Patent number: 12182018
    Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Jayesh Gaur, Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi Feghali
  • Patent number: 12130738
    Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jayesh Gaur, Wajdi K. Feghali, Vinodh Gopal, Utkarsh Kakaiya
  • Patent number: 12086591
    Abstract: Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: Sudhanshu Shukla, Jayesh Gaur, Stanislav Shwartsman, Pavel I. Kryukov
  • Patent number: 12028094
    Abstract: Methods and apparatus relating to an Application Programming Interface (API) for fine grained low latency decompression within a processor core are described. In an embodiment, a decompression Application Programming Interface (API) receives an input handle to a data object. The data object includes compressed data and metadata. Decompression Engine (DE) circuitry decompresses the compressed data to generate uncompressed data. The DE circuitry decompress the compressed data in response to invocation of a decompression instruction by the decompression API. The metadata comprises a first operand to indicate a location of the compressed data, a second operand to indicate a size of the compressed data, a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored, and a fourth operand to indicate a size of the decompressed data. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 2, 2024
    Inventors: Jayesh Gaur, Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi Feghali
  • Patent number: 12020033
    Abstract: Apparatus and method for memorizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memorization based on retiring micro-operations (uops) from a processing pipeline; memorization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memorization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memorization data structure.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: June 25, 2024
    Assignee: Intel Corporation
    Inventors: Niranjan Kumar Soundararajan, Sreenivas Subramoney, Jayesh Gaur, S R Swamy Saranam Chongala
  • Patent number: 11972126
    Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a portion of the metadata region, obtain first metadata stored in the metadata region, use the first metadata to determine an alternate memory address in a relocation region, and read, at the alternate memory address, displaced data from the portion of the metadata region included in the address range of the memory allocation. The address range includes one or more bytes of an expected allocation region of the memory allocation.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael D. LeMay, Sergej Deutsch, Joydeep Rakshit, Anant Vithal Nori, Jayesh Gaur, Sreenivas Subramoney