Patents by Inventor Jayesh R. Bhakta
Jayesh R. Bhakta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8154901Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: April 13, 2009Date of Patent: April 10, 2012Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
-
Patent number: 8081536Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.Type: GrantFiled: February 22, 2011Date of Patent: December 20, 2011Assignee: Netlist, Inc.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
-
Patent number: 8081535Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.Type: GrantFiled: November 24, 2010Date of Patent: December 20, 2011Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon
-
Patent number: 8081537Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.Type: GrantFiled: June 6, 2011Date of Patent: December 20, 2011Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon
-
Patent number: 8072837Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.Type: GrantFiled: December 29, 2010Date of Patent: December 6, 2011Assignee: Netlist, Inc.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
-
Patent number: 8033836Abstract: A circuit includes a first plurality of contacts configured to be in electrical communication with a plurality of electronic devices. The circuit card further includes a flexible portion including a dielectric layer, a second plurality of contacts, and a plurality of electrical conduits extending across a region of the flexible portion and in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible portion further includes an electrically conductive layer extending across the region of the flexible portion. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not overlay one or more portions of the dielectric layer in the region of the flexible portion.Type: GrantFiled: September 2, 2010Date of Patent: October 11, 2011Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Enchao Yu, Chi She Chen, Richard E. Flaig
-
Patent number: 8001434Abstract: A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.Type: GrantFiled: April 13, 2009Date of Patent: August 16, 2011Assignee: NETLIST, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Soonju Choi
-
Patent number: 7965578Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.Type: GrantFiled: November 24, 2010Date of Patent: June 21, 2011Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon
-
Patent number: 7965579Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.Type: GrantFiled: December 29, 2010Date of Patent: June 21, 2011Assignee: Netlist, Inc.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
-
Publication number: 20110110047Abstract: A module is electrically connectable to a computer system. The module includes a first surface and a first plurality of circuit packages coupled to the first surface. The module further includes a second surface and a second plurality of circuit packages coupled to the second surface. The second surface faces the first surface. The module further includes at least one thermal conduit positioned between the first surface and the second surface. The at least one thermal conduit is in thermal communication with the first plurality of circuit packages and the second plurality of circuit packages.Type: ApplicationFiled: November 4, 2010Publication date: May 12, 2011Applicant: Netlist, Inc.Inventors: Robert S. Pauley, Jayesh R. Bhakta, William M. Gervasi, Chi She Chen, Jose Delvalle
-
Publication number: 20110090749Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.Type: ApplicationFiled: November 24, 2010Publication date: April 21, 2011Applicant: Netlist, Inc.Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon
-
Publication number: 20110085406Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.Type: ApplicationFiled: November 29, 2010Publication date: April 14, 2011Applicant: Netlist, Inc.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
-
Patent number: 7916574Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.Type: GrantFiled: November 29, 2010Date of Patent: March 29, 2011Assignee: Netlist, Inc.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
-
Patent number: 7881150Abstract: A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices.Type: GrantFiled: December 2, 2009Date of Patent: February 1, 2011Assignee: Netlist, Inc.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
-
Publication number: 20110016269Abstract: A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.Type: ApplicationFiled: July 16, 2009Publication date: January 20, 2011Inventors: Hyun Lee, Jayesh R. Bhakta
-
Publication number: 20110016250Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.Type: ApplicationFiled: April 15, 2010Publication date: January 20, 2011Applicant: NETLIST, INC.Inventors: Hyun Lee, Jayesh R. Bhakta
-
Patent number: 7864627Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.Type: GrantFiled: October 12, 2009Date of Patent: January 4, 2011Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon
-
Patent number: 7839645Abstract: A module is electrically connectable to a computer system. The module includes a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first surface and a first plurality of circuits coupled to the first surface. The first plurality of circuits is in electrical communication with the electrical contacts. The module further includes a second surface and a second plurality of circuits coupled to the second surface. The second plurality of circuits is in electrical communication with the electrical contacts. The second surface faces the first surface. The module further includes at least one thermally conductive layer positioned between the first surface and the second surface. The at least one thermally conductive layer is in thermal communication with the first plurality of circuits, the second plurality of circuits, and a first set of the plurality of electrical contacts.Type: GrantFiled: October 26, 2009Date of Patent: November 23, 2010Assignee: Netlist, Inc.Inventors: Robert S. Pauley, Jayesh R. Bhakta, William M. Gervasi, Chi She Chen, Jose Delvalle
-
Patent number: 7811097Abstract: A circuit includes a first plurality of contacts configured to be in electrical communication with a plurality of electronic devices. The circuit card further includes a flexible portion including a dielectric layer, a second plurality of contacts, and a plurality of electrical conduits extending across a region of the flexible portion and in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible portion further includes an electrically conductive layer extending across the region of the flexible portion. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not overlay one or more portions of the dielectric layer in the region of the flexible portion.Type: GrantFiled: September 24, 2008Date of Patent: October 12, 2010Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Enchao Yu, Chi She Chen, Richard E. Flaig
-
Publication number: 20100128507Abstract: A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices.Type: ApplicationFiled: December 2, 2009Publication date: May 27, 2010Applicant: NETLIST, INC.Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta