Patents by Inventor Jayesh Vrajlal Sheth

Jayesh Vrajlal Sheth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual bus system with multiple processors having data coherency maintenance
    Patent number: 5809533
    Abstract: A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: September 15, 1998
    Assignee: Unisys Corporation
    Inventors: Dan Trong Tran, Paul Bernard Ricci, Jayesh Vrajlal Sheth, Theodore Curt White, Richard Allen Cowgill
  • Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue
    Patent number: 5737756
    Abstract: A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.
    Type: Grant
    Filed: August 21, 1996
    Date of Patent: April 7, 1998
    Assignee: Unisys Corporation
    Inventors: Theodore Curt White, Jayesh Vrajlal Sheth
  • Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses
    Patent number: 5696937
    Abstract: A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which is filled by a spy module which monitors dual system busses to select addresses of words which appear for write operations.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: December 9, 1997
    Assignee: Unisys Corporation
    Inventors: Theodore Curt White, Jayesh Vrajlal Sheth
  • Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address
    Patent number: 5666515
    Abstract: Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: September 9, 1997
    Assignee: Unisys Corporation
    Inventors: Theodore Curt White, Jayesh Vrajlal Sheth, Kha Nguyen, Dan Trong Tran