Patents by Inventor Jayna Sheats

Jayna Sheats has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230333475
    Abstract: A composite material comprising a release material and a thermopolymer material, and its uses thereof, is described. The composite material may provide improved adhesiveness to components disposed thereon. The composite material may receive a plurality of components from an initial substrate, and may transfer the plurality of components once the initial substrate is removed.
    Type: Application
    Filed: April 13, 2023
    Publication date: October 19, 2023
    Inventors: Jayna Sheats, Matthew Robinson, Dillon M. Love
  • Publication number: 20230144598
    Abstract: A process for transferring a component from a release layer by exposing the release layer to light and heat from different sources is described. The process includes providing an assembly comprising a substrate, a release layer and a component, heating the release layer and exposing the release layer to an actinic wavelength of light, wherein the heating source and the actinic irradiation source are different sources.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 11, 2023
    Inventors: Jayna Sheats, Matthew Robinson
  • Publication number: 20220317559
    Abstract: Intermittently photobleached mask with photobleachable and photobleached regions are described, as well as their fabrication and use to selectively release components from a substrate. Intermittently photobleached mask may allow a plurality of select components to be released simultaneously from a donor plate comprising a release layer, thereby facilitating component transfer.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Inventor: Jayna Sheats
  • Publication number: 20220319829
    Abstract: Assembly and laminates used for or in integrated circuit manufacturing are described, as well as the methods of fabrication and use. The assemblies may include closely spaced components held in place by a release layer or by vacuum applied to a porous substrate, and at least one embedding material deposited to encapsulate the components while leaving the side of the components comprising pads uncoated, thereby forming a laminate of the components and embedding material.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 6, 2022
    Inventor: Jayna Sheats
  • Publication number: 20220319900
    Abstract: Selective donor plates comprising at least one raised “mesa” and a release layer disposed over the top mesa surface are described, as well as their methods of use and their methods of fabrication. The use of selective donor plates including mesas and a release layer may enable reduced standoff distances and misplacement of components, as well as improve assembly time of devices.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 6, 2022
    Inventor: Jayna Sheats
  • Patent number: 9406644
    Abstract: Parallel transfers of components from donor plates to chip modules can be performed with a single alignment step, after arranging the components to have the correct lateral positions. For example, a dimension of the chip module can be separated to be an integer multiple of a period of the component array on the donor plates.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: August 2, 2016
    Assignee: TEREPAC
    Inventors: Yun Uhm, Jayna Sheats
  • Patent number: 9224641
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: December 29, 2015
    Inventor: Jayna Sheats
  • Publication number: 20150155261
    Abstract: Parallel transfers of components from donor plates to chip modules can be performed with a single alignment step, after arranging the components to have the correct lateral positions. For example, a dimension of the chip module can be separated to be an integer multiple of a period of the component array on the donor plates.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 4, 2015
    Inventors: Yun Uhm, Jayna Sheats
  • Publication number: 20150111376
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventor: Jayna Sheats
  • Publication number: 20150053774
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 26, 2015
    Inventor: Jayna Sheats
  • Patent number: 8928118
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 6, 2015
    Inventor: Jayna Sheats
  • Patent number: 8889482
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: November 18, 2014
    Inventor: Jayna Sheats
  • Patent number: 8759713
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process bonds multiple interconnect wires to bond pads with electrical linkages between the bond pads and then subsequently separates the adjacent bond pads.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: June 24, 2014
    Assignee: Terepac Corporation
    Inventor: Jayna Sheats
  • Patent number: 8522848
    Abstract: The present invention relates to methods and apparatuses for assembling substrates with functional blocks, using a printhead to deliver individual functional blocks to the appropriate locations on the substrates. In an embodiment, the functional block releasing mechanism comprises a heat source to provide thermal energy and a light source to provide photon energy, wherein the heat source and the light source enable releasing individual functional blocks from the reservoir for positioning on the substrate. The heat source can comprise an array of heating elements, such as thin film heating elements, which can provide localized heating to individual elements, thus enabling releasing individual functional blocks. The light source can comprise a laser beam and a moving mechanism to move the laser beam to the individual functional blocks.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: September 3, 2013
    Inventor: Jayna Sheats
  • Patent number: 8513110
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides a beveled slope of the components to facilitate interconnection bonding.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: August 20, 2013
    Inventor: Jayna Sheats
  • Patent number: 8387238
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: March 5, 2013
    Inventor: Jayna Sheats
  • Patent number: 8389057
    Abstract: The present invention discloses systems and methods for printing functional blocks from a plurality of printheads to a target substrate. In exemplary embodiments, the printing system comprises a main printhead for the majority of printing process, and a secondary printhead for supplemental printing. The system further comprises a controller, utilizing a positioning intelligence system to distribute the printing of the functional blocks between the main printhead and the secondary printhead, to minimize the motions of the printheads while maximize the printing speed.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: March 5, 2013
    Inventors: Douglas Knox, Jayna Sheats, Ric Asselstine
  • Patent number: 8247243
    Abstract: Methods and devices for solar cell interconnection are provided. In one embodiment, the method includes physically alloying the ink metal to the underlying foil (hence excellent adhesion and conductivity with no pre-treatment), and by fusing the solid particles in the ink on the surface (eliminating any organic components) so that the surface is ideally suited for good conductivity and adhesion to an overlayer of finger ink, which is expected to be another adhesive. In some embodiments, contact resistance of conductive adhesives are known to be much lower on gold or silver than on any other metals.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: August 21, 2012
    Assignee: Nanosolar, Inc.
    Inventors: Jayna Sheats, Phil Stob
  • Patent number: 8153517
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: April 10, 2012
    Assignee: Terepac Corporation
    Inventor: Jayna Sheats
  • Patent number: 8124452
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The process can separate the integrated circuits into an analog portion and a digital portion with the analog portion comprising passive components utilizing dielectric materials different than silicon dioxide and active components utilizing channel materials different than substrate single crystal silicon.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: February 28, 2012
    Assignee: TEREPAC Corporation
    Inventor: Jayna Sheats