Abstract: A system for electroplating integrated circuit wafers includes an electroplating solution containment chamber having a first end that is capable of supporting an integrated circuit wafer so that a surface of the wafer faces an internal volume of the chamber, and a second end opposing the first end across the internal volume. The system further includes a liquid directing element at the second end. The liquid directing element includes a plurality of channels having divergent axes so as to direct a helical flow of electroplating solution toward the surface of the integrated circuit wafer when the wafer is present and the liquid directing element is attached to a source of pressurized electroplating solution.

Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.

Abstract: A semiconductor wafer having copper bondpads (17) that are free of voids (13) and a method for coating the copper bondpads (17) with solderable or wirebondable metals such that the copper bondpads (17) are free of the voids (13). The void free metal coatings are achieved using a dual activation process. In a first activation step (27), the copper bondpads (17) are activated by placing them in a palladium bath. In a second activation step (28), the bondpads are placed in a nickel—boron bath. After the dual activation, the copper bondpads (17) are coated with a layer of nickel—phosphorous or palladium. The nickel—phosphorous or palladium layer may be coated with a layer of gold for subsequent formation of solder balls or wirebonds thereon.

Abstract: A semiconductor wafer having copper bondpads (17) that are free of voids (13) and a method for coating the copper bondpads (17) with solderable or wirebondable metals such that the copper bondpads (17) are free of the voids (13). The void free metal coatings are achieved using a dual activation process. In a first activation step (27), the copper bondpads (17) are activated by placing them in a palladium bath. In a second activation step (28), the bondpads are placed in a nickel-boron bath. After the dual activation, the copper bondpads (17) are coated with a layer of nickel-phosphorous or palladium. The nickel-phosphorous or palladium layer may be coated with a layer of gold for subsequent formation of solder balls or wirebonds thereon.

Abstract: According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

Abstract: The present invention provides a novel method for forming uniform dendrites, on circuit features that does not result in large, elongated dendrites along the edges of the circuit features. The method comprises the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry.

Abstract: An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.

Abstract: The present invention provides uniform dendrites, on circuit features instead of large, elongated dendrites along the edges of the circuit features. The dendrites are formed by a method comprising the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry.

Abstract: According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

Abstract: Dielectric adhesive film patterned with clusters of electrically conductive filaments that extend through the film thickness for providing electrical interconnection and encapsulation. The dielectric adhesive material is reworkable. The clusters are formed by selectively electroplating a noble metal at a high current density.

Abstract: A technique of connecting a first member having a first face to a second member having a second face utilizing dendrites is provided. Dendrites are formed on one face of the first member in a given configuration. Dendrite receiving and securing material, preferably solder, is formed on a face of the second member in a configuration confirming substantially to the given configuration of the dendrites on the one face. The first and second members are then placed in a position relative to each other with the dendrites on the one face of the first member in contact with the dendrite receiving and engaging material on the face of the second member. An airtight seal is then provided between the first and second faces surrounding the dendrites and dendrite receiving and engaging material, which forms a sealed chamber between the first and second members.