Patents by Inventor Jaynarayan H. Lala

Jaynarayan H. Lala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6018812
    Abstract: Wafer scale integrated circuitry which uses a cluster of wafer components, each component having a plurality of processing elements and a network element connected thereto for controlling the transfer of information to and from the processing elements. The network element is connected to network elements of other wafer components of the cluster for controlling the transfer of information to and from such other network elements. One or more redundant groups of processing elements are formed on the wafer components of the cluster, each redundant group being configured so that the processing elements in the group reside on different ones of the wafer components.
    Type: Grant
    Filed: October 17, 1990
    Date of Patent: January 25, 2000
    Assignee: 501 Charles Stark Draper Laboratory, Inc.
    Inventors: John J. Deyst, Jr., Richard E. Harper, Jaynarayan H. Lala
  • Patent number: 5210871
    Abstract: A method for resolving access contentions by a plurality of processing sites having the same or different redundancies to a shared communications system wherein the start of the access contention process is first synchronized for all contending sites. A determination is then made of which sites are performing tasks of the highest criticality level and a subsequent determination is made as to which of such highest criticality sites has the highest priority level. Access is then provided to the site having the highest priority level.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: May 11, 1993
    Assignee: The Charles Stark Draper Labroatory, Inc.
    Inventors: Jaynarayan H. Lala, Stuart J. Adams
  • Patent number: 4937741
    Abstract: A system for synchronizing the operation of a plurality of redundant processors forming groups thereof in which a frame of operation is defined as a time period during which a selected number of processing events occurs. For each processor, the performance of a first one of such events specifies the start of a frame and the performance of the last one of such events specifies the end of a frame. When the final event is performed by the last-to-perform of the processors of a group, the operations of all the processors of the group are then synchronized to start the next frame of operation at substantially the same time. The processors have execution rates which lie within the specified range thereof, the processors must perform their final events within a specified time period, and the processors of a group are arranged so as to start a frame of operation within another specified time period.
    Type: Grant
    Filed: April 28, 1988
    Date of Patent: June 26, 1990
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Richard E. Harper, Jaynarayan H. Lala
  • Patent number: 4907232
    Abstract: A fault tolerant processing system which includes a plurality of at least (3f+1) fault containment regions each including a plurality of processors and a network element connected to each of the processors and to the network elements of the other regions. Groups of processors are used to form redundant processing sites, the number of each group being included in a different fault containment region. The operations of the network elements are synchronized and the system can be arranged to re-configure the groups of processors so as to form different pluralities of redundant processing sites.
    Type: Grant
    Filed: April 28, 1988
    Date of Patent: March 6, 1990
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Richard E. Harper, Jaynarayan H. Lala
  • Patent number: 4665522
    Abstract: A multi-channel redundant processing system having tightly synchronized redundant processor channels wherein one or more additional processors are connected to each of the redundant channels, the redundant outputs being supplied to such additional processors to permit different processing operations to be performed on such redundant outputs. A selected number of added processors can perform the same processing operations and the processed outputs can be supplied to the redundant processor channels to establish a selected degree of reliability while one or more other added processors can be used to perform other processing operations on the redundant outputs in a non-redundant manner. Further, such added processors can be used to detect software programs fault situations in which multiple versions of software programs are used.
    Type: Grant
    Filed: January 28, 1985
    Date of Patent: May 12, 1987
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Jaynarayan H. Lala, Larry D. Brock