Abstract: An optical transmit and receive circuit that includes a single control module that controls the transmit and receive operational behaviors in multiple transmit and receive data paths of the optical transmit and receive circuit. By having a single control module control operational behaviors of multiple electro-optic transducer drivers, and multiple post-amplifiers, the size of the overall combination may be reduced.

Abstract: A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver.

Abstract: An optical transceiver (or optical transmitter or optical receiver) that is coupled to a host computing system. The optical transceiver includes a system memory and at least one processor. The optical transceiver operates at least in part by the processor executing microcode from system memory. In order to change operation, the optical transceiver pages microcode segments from the host computing system to the system memory of the optical transceiver to adjust for changing operational circumstances. For example, by this paging, microcode segments that are more likely to be used given the current operational circumstances are loaded into the system memory of the optical transceiver, while microcode segments that are less likely to be used given the current operational circumstances are retained at the host computing system.

Abstract: An optical transceiver host computing system (hereinafter simply referred as the “host”) printed circuit board has multiple optical transceivers directly mounted to it. Each optical transceiver is configured to convert an electrical signal into an optical signal and to transmit the optical signal and to receive an optical signal and convert the received signal into an electrical signal. By directly mounting the optical transceivers to the host printed circuit board, an increased number of transceivers may be supported by a single host without increasing the overall size of the host.

Abstract: An operational optical transceiver configured to self-validate a boot image loaded from the persistent memory early in the boot process. The optical transceiver includes a persistent memory, a controller, and a system memory. The controller initializes the boot process and begins to load information from the persistent memory to the system memory. Next, the controller detects early in the boot process boot image verification data in the information being sent to the system memory. The controller then determines if the boot image verification data has an expected value. If the verification data includes the expected value, the controller continues the boot process. If the verification data does not include the expected value, the controller will retry the boot process a predetermined number of times and will enter a default operational state if the expected value is not detected while retrying the boot process the predetermined number of times.

Abstract: An optical transceiver (or transmitter or receiver) that uses microcode that represents a formulaic relation between temperature and an appropriate value for an operational parameter given the temperature. The microcode is further structured such that when loaded into system memory and executed by the optical transceiver, the optical transceiver accesses the temperature as measured by a temperature sensor, calculates an appropriate value for the operational parameter given the accessed temperature using the formulaic relation, and adjusts the operational parameter according to the calculation. This allows the optical transceiver to adjust temperature-dependent operational parameters using less memory than required to perform a table-based representation of temperature versus the operational parameter.

Abstract: A method that enables an optical transceiver to perform consistency checking, such as Cyclic Redundancy Checking (CRC), over internal information stored in the transceiver's memory while the transceiver is in operation. The optical transceiver includes a system memory and a consistency checker component. The consistency checker component determines that consistency checking is to be performed and identifies which portion of the system memory is to be checked. The consistency checker reads the portion of system memory and determines whether or not the portion of system memory is consistent with an expected consistency check value.

Abstract: An optical transceiver that custom logs information based on input from a host computing system (hereinafter referred to as a “host”). The optical transceiver receives input from the host concerning which operational information to log; the operational information may include statistical data about system operation, or measured parameters, or any other measurable system characteristic. The input from the host may also specify one or more storage locations corresponding to the identified operational information. If one or more storage locations are specified, the optical transceiver logs the information to the corresponding storage locations, which may be an on-transceiver persistent memory, the memory of the host or any other accessible logging location. Additionally, the input from the host may specify one or more actions to be performed when the identified information is logged. If one or more actions are specified, the optical transceiver performs the specified actions when the information is logged.

Abstract: An operational optical transceiver microcontroller configured to initiate a self-test using internalized loop backs. The microcontroller includes a memory, at least one processor and a number of input and output terminals. The output terminals are coupled to internally corresponding input terminals by a configurable switch. The memory receives microcode that, when executed by the processor, causes the microcontroller to close the switches so as to internally connect the output and input terminals. A signal is then asserted on the output terminal. This signal loops back and is received by the input terminal. The processor may then detect the microcontroller's response to the signal.

Abstract: An optical transceiver (or optical transmitter or optical receiver) that has at least one processor and a memory. The optical transceiver receives encrypted microcode from a source. The optical transceiver may then decrypt the received microcode to create decrypted microcode. The decrypted microcode is then written to the memory, where it may be executed by the at least one processor. The microcode, when executed by the at least one processor, controls one or more functions of the optical transceiver.

Abstract: An optical transceiver (or optical transmitter or optical receiver) that has at least one processor, and a memory. The optical transceiver is capable of implementing any one of a number of protocols depending on how the optical transceiver is configured in microcode. In order to so configure the optical transceiver, the optical transceiver is provided with one of a particular set of microcode, each of the set of microcode being capable of implementing a different protocol when received into the memory and executed. To implement the protocol, the provided microcode is then executed by the optical transceiver. To implement a different protocol, different microcode may be provided to the optical transceiver and executed.

Abstract: A method that enables an optical transceiver (or optical transmitter or optical receiver) to perform consistency checking such as Cyclic Redundancy Checking (CRC) in the background while the transceiver is in operation. The optical transceiver includes a system memory and a consistency checker component. The optical transceiver determines that consistency checking is to be performed and identifies non-contiguous static portions of the system memory to be checked. The consistency checker reads the non-contiguous static portions of system memory and determines whether or not the portions of system memory are consistent with an expected consistency check value.

Abstract: An operational optical transceiver configured to preserve a portion of volatile memory during a warm reboot process. The optical transceiver includes a persistent memory, a processor, and a system memory. The system memory includes a preserved memory space. The optical transceiver loads microcode from the persistent memory to the system memory without writing into the preserved memory space. The processor processes the microcode and writes certain information into the preserved memory space that will be preserved during a warm reboot. The optical transceiver may then initiate a warm reboot and load microcode from the persistent memory to the system memory that overwrites the existing microcode. However, the information written in the preserved memory space is not overwritten by the microcode loaded from the persistent memory. In this way, a portion of the information contained in the system memory prior to the warm reboot is preserved.

Abstract: A method for changing the host communication interface address for a number of individual optical transceivers sharing a single host communication interface. An optical transceiver host computing system is communicatively coupled to the transceivers using the single host communication interface. The host computing system implements the host interface address change by indicating to a first transceiver that an address change is pending. The host then informs the first transceiver that it is to have its address changed using a mechanism independent of the addressing mechanism used by the signal host communication interface. In response, the first transceiver makes the address change. The other optical transceivers may have their address changed using the same method, although this is not required.

Abstract: An operational optical transceiver configured to dynamically adjust the boot speed of the optical transceiver boot process. The optical transceiver includes a persistent memory, a system memory, and a controller configured to load information from the persistent memory to the system memory. The controller initiates the boot process at a slower boot speed and begins to load information from the persistent memory to the system memory. The controller then detects boot speed data in the information being loaded to the system memory that defines a faster boot speed. In response to the detected boot speed data, the controller continues the boot process by loading additional information from the persistent memory to the system memory at a second boot speed that is faster than the first boot speed.

Abstract: An optical transceiver (or transmitter or receiver) that uses microcode and an internal sensor to self-calibrate itself to an environmental parameter such as, for example, temperature. In particular, the optical transceiver senses the environmental parameter under changing environmental circumstances. The optical transceiver then calculates how an operational parameter such as laser bias current should change based on the sensing operation. The optical transceiver then persistently records an approximation of the relation between the environmental parameter and the operational parameter. This approximation may later be used during operation to adjust the operational parameter as appropriate given then-existing environmental circumstances.

Abstract: A method for dynamically updating an optical transceiver (or optical transmitter or optical receiver) that has at least one processor and persistent memory that includes one or more write-protected memory locations. The write-protected memory locations of the persistent memory includes loader microcode that, when executed by the at least one processor, causes the optical transceiver to have access to a first set of functionality. In order to implement the invention, the optical transceiver first processes received microcode. Then, the processed representation of the received microcode is written to the persistent memory outside of the one or more write-protected memory locations. The optical transceiver then determines that all of the microcode that is to be written to the persistent memory during the update has been written to the persistent memory. Finally, the persistent memory is altered to reflect that the update is complete.

Abstract: An optical transceiver configured to transmit and receive optical signals. The optical transceiver includes a control module and a persistent memory. The control module is configured to identify operational information regarding the optical transceiver, and write log information representing the operational information to the persistent memory. The operation information may include statistical data about operation, or may include measured parameters. Log entries may be made periodically and/or in response to events. The log may then be evaluated to determine the conditions under which the transceiver has historically operated.

Abstract: Watchdog instructions embedded within the actual microcode that is executed by the processor. Accordingly, as the processor reads and executes the microcode, the processor occasionally encounters the watchdog instruction. Each time the processor executes the watchdog instruction, the processor generates a watchdog signal. A watchdog signal detection circuit detects the presence of the periodic signal. If the watchdog signal has not occurred when expected, then some instability has likely occurred. Accordingly, the watchdog signal detection circuit causes some corrective action to be taken when a watchdog signal is not detected when expected. Such corrective action may include, for example, rebooting the system or resetting one or more modules of the system. The inclusion of the watchdog instruction within the microcode increases the chance that the watchdog signal will be an accurate predictor of system stability.

Abstract: A microcode-initiated high speed comparator in an optical transceiver includes an initialization and control section consisting of various register sets, an analog section with comparator hardware, and an output retrieval section. The comparator hardware performs comparison on a wide-range of selectable input values, thereby avoiding the need for a dedicated comparator for each input value. The register sets are initialized by microcode with various comparison values, allowing multiplexed comparison to be much faster than it would be if the processor was controlling in real-time the multiplexed comparison. The comparison values may correspond to optimal operational parameters of the optical transceiver or may correspond to other desired comparison values. The analog section is driven by the registers and makes a comparison between the predetermined values and actual operational parameter values.