Abstract: In methods of manufacturing an image device, a first structure including a transparent lower portion and an opaque upper portion is formed on a substrate having a photodiode. An etch stop layer pattern positioned over the photodiode is formed on the first structure. A second structure having at least one opaque capping layer is formed on the first structure to cover the etch stop layer pattern. An opening partially exposing the lower portion of the first structure is formed over the photodiode by etching the second structure, the etch stop layer pattern and the opaque upper portion of the first structure.

Abstract: A semiconductor device may include a fuse pattern and an interconnection pattern formed on a surface of a semiconductor substrate. An interlayer dielectric layer may be disposed on the surface of the semiconductor substrate including the fuse pattern and the interconnection pattern. A bonding pad may be formed over the interconnection pattern and connected to the interconnection pattern through the interlayer dielectric layer. A visible indicator may be formed in the interlayer dielectric layer near the bonding pad. The visible indicator may indicate a bonding region and a probing region of the bonding pad.

Abstract: A method for forming a fuse includes forming an interconnection pattern and a fuse pattern on a substrate using a damascene process. A passivation layer is formed on a surface of the substrate over the interconnection pattern and the fuse pattern. Then, the passivation layer is patterned to form a pad opening that exposes a portion of the interconnection pattern. A metal pad is formed on the interconnection pattern in the pad opening. A portion of the metal pad extends over the passivation layer. The passivation layer on the fuse pattern is partially etched to form a fuse opening.

Abstract: In methods of manufacturing an image device, a first structure including a transparent lower portion and an opaque upper portion is formed on a substrate having a photodiode. An etch stop layer pattern positioned over the photodiode is formed on the first structure. A second structure having at least one opaque capping layer is formed on the first structure to cover the etch stop layer pattern. An opening partially exposing the lower portion of the first structure is formed over the photodiode by etching the second structure, the etch stop layer pattern and the opaque upper portion of the first structure.

Abstract: An interconnection structure includes a substrate containing a first lower interconnection and a pair of second interconnections separated from each other by a predetermined distance, and a metallic compound fuse pattern connecting the second lower interconnections, being positioned over the second lower interconnections. The fuse pattern is formed by using an upper electrode layer of a capacitor which is relatively thinner, without other interconnections involved in signal propagation speed, having reduced thickness regardless of increasing thickness of interconnections.

Abstract: A method for forming a fuse includes forming an interconnection pattern and a fuse pattern on a substrate using a damascene process. A passivation layer is formed on a surface of the substrate over the interconnection pattern and the fuse pattern. Then, the passivation layer is patterned to form a pad opening that exposes a portion of the interconnection pattern. A metal pad is formed on the interconnection pattern in the pad opening. A portion of the metal pad extends over the passivation layer. The passivation layer on the fuse pattern is partially etched to form a fuse opening.