Patents by Inventor Jchung-Chang Chen

Jchung-Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    Patent number: 7071100
    Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: July 4, 2006
    Inventors: Kei-Wei Chen, Jung-Chih Tsao, Chi-Wen Liu, Jchung-Chang Chen, Shih-Tzung Chang, Shih-Ho Lin, Yu-Ku Lin, Ying-Lang Wang
  • Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    Publication number: 20050191855
    Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 1, 2005
    Inventors: Kei-Wei Chen, Jung-Chih Tsao, Chi-Wen Liu, Jchung-Chang Chen, Shih-Tzung Chang, Shih-Ho Lin, Yu-Ku Lin, Ying-Lang Wang