Patents by Inventor Je Bong Kang

Je Bong Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6407446
    Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: June 18, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Bong Kang, Jae Won Lee, Heui Seog Kim
  • Publication number: 20010006250
    Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 5, 2001
    Inventors: Je Bong Kang, Jae Won Lee, Heui Seog Kim
  • Patent number: 6031281
    Abstract: Semiconductor devices having bonding wires are encapsulated in a fluid molding resin, and the flow front of the molding resin can displace the bonding wires and create a short of the device. A semiconductor IC device is provided with dummy bonding wires to prevent or reduce the wire displacement by blocking the remaining bonding wires from direct exposure to the molding resin flow front in the mold cavity. Wire displacement or sweep of the dummy bonding wires causes the dummy bonding wires to contact their adjacent remaining bonding wires, but this contact does not cause a short in the device. The size of the semiconductor IC device is thereby reduced by increasing the allowable length of the bonding wires in the device, resulting in improved yields and lower production costs.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: February 29, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Bong Kang, Young Yee Song, Si Chan Sung
  • Patent number: 5923092
    Abstract: A semiconductor IC device requiring dense arrangements of I/O connections in which a plurality of electrode pads are arranged in a rectangular form for a quad surface mounting type package, corner electrode pads are arranged to be shifted toward inside of a semiconductor chip for reducing the distance of corner bonding wires, or corner inner leads are bent and further extended toward the chip for making shorter the span length of the corner bonding wires, so that wire sweeping and electrical shorting of the corner bonding wires during a wire bonding and a molding processes can be prevented and the reliability of the bonding wires can be improved.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: July 13, 1999
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Je Bong Kang