Patents by Inventor Je-Hsiung Lan

Je-Hsiung Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250247076
    Abstract: A device includes a resonator stack. The resonator stack includes a first chiplet including a first acoustic resonator having a first resonant frequency and a second chiplet including a second acoustic resonator having a second resonant frequency that is different from the first resonant frequency. The device also includes a substrate coupled to the resonator stack, and electrical interconnections between the first chiplet and the second chiplet to provide a conductive path between the first acoustic resonator and the second acoustic resonator.
    Type: Application
    Filed: January 25, 2024
    Publication date: July 31, 2025
    Inventors: Jonghae KIM, Je-Hsiung LAN, Ranadeep DUTTA
  • Publication number: 20250226365
    Abstract: A packaged integrated circuit device includes a die that includes integrated radio frequency (RF) circuitry. The packaged integrated circuit device also includes a package substrate including metal layers electrically connected to the RF circuitry. The packaged integrated circuit device further includes an impedance adapter electrically connected to the RF circuitry and disposed between the die and the package substrate. The impedance adapter includes a passive component disposed on or in a body of the impedance adapter.
    Type: Application
    Filed: January 8, 2024
    Publication date: July 10, 2025
    Inventors: Je-Hsiung LAN, Jonghae KIM, Ranadeep DUTTA
  • Patent number: 12354948
    Abstract: A device comprising a die substrate, a plurality of interconnects located over the die substrate, wherein the plurality of interconnects are configured to operate as an inductor, at least one magnetic layer that surrounds at least part of the plurality of interconnects; and at least one dielectric layer that surrounds the at least one magnetic layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 8, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kai Liu, Roy Chiu, Nosun Park, Je-Hsiung Lan, Jonghae Kim
  • Publication number: 20250216623
    Abstract: An interposer has a first side and a second side and includes an optical waveguide defined in a region between the first side and the second side. The interposer also includes first contacts on the first side configured to be electrically connected to one or more electronic devices, and second contacts on the second side configured to be electrically connected to one or more photonic devices. The interposer also includes conductive interconnects electrically connecting one or more of the first contacts to one or more of the second contacts. The interposer also includes an optical coupler on the second side configured to enable coupling of light between the one or more photonic devices and the optical waveguide.
    Type: Application
    Filed: January 3, 2024
    Publication date: July 3, 2025
    Inventors: Ranadeep DUTTA, Jonghae KIM, Je-Hsiung LAN
  • Publication number: 20250210852
    Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.
    Type: Application
    Filed: March 5, 2025
    Publication date: June 26, 2025
    Inventors: Ranadeep Dutta, Jonghae Kim, Je-Hsiung Lan
  • Patent number: 12334903
    Abstract: A substrate that includes an encapsulation layer, a first acoustic resonator, a second acoustic resonator, at least one first dielectric layer, a plurality of first interconnects, at least one second dielectric layer, and a plurality of second interconnects. The first acoustic resonator is located in the encapsulation layer. The first acoustic resonator includes a first piezoelectric substrate comprising a first thickness. The second acoustic is located in the encapsulation layer. The second acoustic resonator includes a second piezoelectric substrate comprising a second thickness that is different than the first thickness. The at least one first dielectric layer is coupled to a first surface of the encapsulation layer. The plurality of first interconnects is coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 17, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Je-Hsiung Lan, Ranadeep Dutta
  • Patent number: 12283607
    Abstract: A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 22, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Je-Hsiung Lan, Ranadeep Dutta
  • Publication number: 20250096093
    Abstract: A package comprising an interposer comprising a silicon substrate comprising a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to the interposer through a first plurality of solder interconnects.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Ranadeep DUTTA, Jonghae KIM, Je-Hsiung LAN
  • Publication number: 20250096116
    Abstract: A device is described, in which the device includes a substrate. The device includes a multiturn inductor coupled to the substrate. The device also includes a patterned ground shield on a periphery of the multiturn inductor and coupled to the substrate.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Jonghae KIM, Je-Hsiung LAN, Ranadeep DUTTA
  • Publication number: 20250096090
    Abstract: An integrated device comprising a die substrate comprising a porous portion; a plurality of through substrate vias extending through the porous portion of the die substrate; and a die interconnection portion coupled to the die substrate.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Ranadeep DUTTA, Jonghae KIM, Je-Hsiung LAN
  • Patent number: 12255381
    Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: March 18, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Ranadeep Dutta, Jonghae Kim, Je-Hsiung Lan
  • Publication number: 20250047262
    Abstract: An acoustic device includes circuit elements, such as analog circuit components, between the first and second substrate and coupled to an acoustic resonator to form an acoustic filter within the acoustic device. In some examples, forming the circuit elements between the first substrate and the second substrate includes forming the first circuit elements in insulating material on the second substrate before coupling the second substrate to a first side of the first substrate. The circuit elements disposed between the first and second substrates may include capacitors, inductors, and electrical interconnects coupled to the acoustic resonator on the first substrate. Additional features may be included in the insulating material. The acoustic device avoids the need for bulky analog components coupled to the acoustic resonator via long interconnects through a package substrate, making it possible to reduce an acoustic device's package size.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Je-Hsiung Lan, Jonghae Kim, Ranadeep Dutta
  • Publication number: 20250037923
    Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The substrate comprises at least one magnetic layer, at least one dielectric layer; and a plurality of interconnects. The plurality of interconnects comprise a first set of interconnects that are configured to operate as a first inductor and a second set of interconnects that are configured to operate as a second inductor. The second inductor and the first inductor are configured to operate as inductively coupled inductors.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventors: Kai LIU, Jui-Yi CHIU, Jonghae KIM, Nosun PARK, Je-Hsiung LAN
  • Patent number: 12206155
    Abstract: In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounte
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: January 21, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kai Liu, Jonghae Kim, Jui-Yi Chiu, Nosun Park, Je-Hsiung Lan
  • Publication number: 20250022858
    Abstract: A device comprising (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as an inductor.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Kai LIU, Jui-Yi CHIU, Jonghae KIM, Je-Hsiung LAN, Nosun PARK
  • Publication number: 20240421790
    Abstract: A package includes a device that includes electrodes disposed on a piezoelectric layer on a first, front side of a first substrate and vertical interconnect accesses (vias) that extend through the substrate to couple the electrodes to a second, back side of the first substrate. The vias may be through-substrate vias (TSVs). Employing a first substrate (e.g., silicon) in which vias can be formed, the electrodes on the front side can be coupled to interconnects on the back side to minimize electrical path distances to and from the device for a higher a Q factor. Also, a capacitor may be formed on a second, back side of the substrate and coupled to an electrode of the device by a via rather than having an electrical path from a first substrate, to an external capacitor on a package substrate. A thermal conductive path is also reduced for improved heat dissipation.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Je-Hsiung Lan, Jonghae Kim, Ranadeep Dutta
  • Patent number: 12155373
    Abstract: Disclosed is a radio frequency (RF) filter that vertically integrates an acoustic die with inductors formed in one or more layers above the acoustic die. The acoustic die may be over-molded so that the acoustic dome, important for maintaining acoustic integrity, may be protected.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: November 26, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kai Liu, Je-Hsiung Lan, Jonghae Kim
  • Publication number: 20240387092
    Abstract: An inductive device includes multiple packaged devices, each including a body and a conductor layer within the body and a set of external connectors. The conductor layer of a packaged device includes a set of conductive lines electrically connected to the set of external connectors of the packaged device. Conductive lines of two packaged devices of the inductive device are at an angle relative to one another. External connectors of the packaged devices are coupled to one another to electrically connect the sets of conductive lines to define one or more coils, each coil having multiple turns and each turn including a conductive line of each packaged device.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Inventors: Kai LIU, Jui-Yi CHIU, Jonghae KIM, Nosun PARK, Je-Hsiung LAN
  • Patent number: 12142561
    Abstract: An integrated device that includes a die substrate comprising a plurality of transistors, an interconnection portion coupled to the die substrate, and a packaging portion coupled to the interconnection portion. The interconnection portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: November 12, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kai Liu, Je-Hsiung Lan, Jonghae Kim
  • Publication number: 20240347913
    Abstract: An antenna module as a radio-frequency (RF) integrated circuit (IC) semiconductor die (“die”) with an integrated antenna substrate. The die with the integrated antenna substrate can be provided as part of a single IC chip that is fabricated as part of a wafer-level fabrication process as an example. The antenna elements are formed in one more antenna layers as part of an antenna substrate. The antenna layers may be formed as re-distribution layers (RDLs) for example to support smaller line-spacing (LS) and/or smaller pitched metal interconnects for forming and interconnecting to smaller wavelength antenna elements for supporting higher frequency communications. The antenna substrate is formed on a semiconductor wafer of an IC as part of the die. In this manner, the antenna layers can be formed as part of a wafer-level fabrication process used to form the die to form the antenna layers.
    Type: Application
    Filed: April 13, 2023
    Publication date: October 17, 2024
    Inventors: Ranadeep Dutta, Jonghae Kim, Je-Hsiung Lan