Abstract: A communication device and method of controlling an operation of a communication device are provided, by which an application can be efficiently selected according to location information. The communication device includes a wireless communication unit for determining a location using received information, a controller for generating location information based on the determined location and searching for an application corresponding to the location information, and a display for displaying an indicator of the searched application.

Abstract: A communication device and method of controlling an operation of a communication device are provided, by which an application can be efficiently selected according to location information. The communication device includes a wireless communication unit for determining a location using received information, a controller for generating location information based on the determined location and searching for an application corresponding to the location information, and a display for displaying an indicator of the searched application.

Abstract: A communication device and method of controlling an operation of a communication device are provided, by which an application can be efficiently selected according to location information. The communication device includes a wireless communication unit for determining a location using received information, a controller for generating location information based on the determined location and searching for an application corresponding to the location information, and a display for displaying an indicator of the searched application.

Abstract: A communication device and method of controlling an operation of a communication device are provided, by which an application can be efficiently selected according to location information. The communication device includes a wireless communication unit for determining a location using received information, a controller for generating location information based on the determined location and searching for an application corresponding to the location information, and a display for displaying an indicator of the searched application.

Abstract: Disclosed herein is an apparatus and method for controlling the travel speed of a vehicle using information about a road or at least one portion thereof ahead of the vehicle. The apparatus includes a forward image sensor for photographing a forward road or portion(s) thereof, acquiring image data, and extracting information about the forward road or portion(s) from the image data using a Kalman filter. A control unit calculates a target speed required for the vehicle to travel using the forward road information. With the apparatuses and methods, vehicle safety and driving comfort can be improved.

Abstract: The lane deviation warning system is provided, including a traveling lane detection unit for detecting a traveling lane; an operation detection unit connected to at least a sensor and for detecting motion of the vehicle in real time; a controller for controlling to calculate and output a traveling lane deviation time point of the vehicle according to data detected through the traveling lane detection unit and the operation detection unit by setting at least a critical line of the traveling lane based on data detected through the traveling lane detection unit, and to output a corresponding warning signal when the vehicle reaches at least a preset critical line; and a warning device driver for controlling to drive at least one of a first warning means and a second warning means according to a warning signal output from the controller.

Abstract: A clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device. The clock generator includes a clock input circuit receiving an external clock signal, a reference voltage signal and an option signal, and outputting first and second clock signals; a clock driver receiving the first clock signal and outputting an internal clock signal in response to the option signal; and a detector receiving the second clock signal and outputting the option signal in response to a control signal.

Abstract: A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.

Abstract: A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.

Abstract: A clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device. The clock generator includes a clock input circuit receiving an external clock signal, a reference voltage signal and an option signal, and outputting first and second clock signals; a clock driver receiving the first clock signal and outputting an internal clock signal in response to the option signal; and a detector receiving the second clock signal and outputting the option signal in response to a control signal.

Abstract: A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.

Abstract: 1. An apparatus for outputting data included in a synchronous memory device includes: first storage unit for storing in sequence even data provided by a first sense amplifier coupled to a selected even bank; second storage unit for storing odd data in sequence provided by a second sense amplifier coupled to a selected odd bank; selection unit coupled to the first storage unit and the second storage unit, for receiving at the same time both the even data and the odd data; third storage unit for storing and providing one of both the even data and the odd data in synchronization with a rising edge of a clock signal; fourth storage unit for storing and providing one of both the even data and the odd data in synchronization with a falling edge of a clock signal; data output unit for driving data from third storage unit and data from the fourth storage unit.

Abstract: A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.

Abstract: Disclosed is a semiconductor memory device to reduce the number of address bus lines. The semiconductor memory device according to the present invention includes a common data bus line, a plurality of address buffers coupled to the common data bus line for buffering external address signals, a refresh counter coupled to the common data bus line, including a buffer for providing refresh address signals, a first controller for selectively transferring the external address signals buffered in the address buffers to the common data bus line, and a second controller for selectively transferring the refresh address signals from the refresh counter to the common data bus line.

Abstract: A semiconductor memory device, includes: an external address buffer for buffering a first address signal to generate a buffered address signal; a delay for delaying the buffered address signal for a predetermined time to generate a delayed address signal; an internal address buffer for buffering the buffered address signal and the delayed address signal to generate a second address signal; a common address bus line; a switching unit responsive to a control signal for selectively coupling one of the buffered address signal, the delayed address signal and the second address signal as a selected address signal to said common address bus line; and a column predecoder for predecoding the selected address signal transferred via said common address bus line.

Abstract: A semiconductor memory device includes a transmission line, connected to a driving unit, for transmitting a signal from the driving unit, a delaying unit for delaying a level of the transmission line to output the delayed signal, a precharging unit for receiving the delayed signal to precharge the transmission line, and a stabilization unit for accelerating the level transition of the transmission line, wherein the stabilization unit includes a detecting unit for detecting the level of the transmission line transmitted from the driving unit to generate a detected signal, and a switching unit for performing a switching operation in response to the detected level to swiftly achieve a level transition of the transmission line.

Abstract: A write driver circuit with a write-per-bit data masking function, comprising a masking register for inputting data to be written in a memory cell and generating masking data with respect to the input data, a first output controller for determining masking of the input data in response to an output signal from the masking register, a second output controller for determining masking of an inverted one of the input data in response to the output signal from the masking register, and an output unit for transferring output data from the first and second output controllers to data input/output lines of a memory device. According to the present invention, a WPB data masking operation is not performed at the column active step but at the row active step. Therefore, a write speed is enhanced by removing a conventional write delay time resulting from the execution of the WPB data masking operation at the column active step.