Abstract: Provided is a reflective intelligent reflecting surface (IRS) flexible board, which includes: a flexible film; and a plurality of unit cells formed on the flexible film, in which each of the plurality of unit cells includes an IC for adjusting a reflection phase, a line pattern for driving the IC, and first and second antenna patterns formed symmetrically to each other based on the IC or the line pattern.

Abstract: Provided is a method for transmitting power in wireless communication using reconfigurable intelligent reflecting surfaces (RIS) of an electronic device, which includes: determining a value of a reflection coefficient of each unit cell or tile by scanning each tile of a reconfigurable intelligent reflecting surface (RIS) by a signal radiated through a transmitter; sending a beam to the reconfigurable intelligent reflecting surface (RIS) by controlling the transmitter; and multi-focusing an electromagnetic wave signal incident on the reconfigurable intelligent reflecting surface (RIS) on a plurality of receivers by setting an on/off state in each unit cell of the reconfigurable intelligent reflecting surface (RIS) based on the determined control parameter value, in which the tile is a partial array of the RIS having the same size, and supports far-field communication for the plurality of receivers.

Abstract: Provided is a reflective intelligent reflecting surface (IRS) flexible board, which includes: a flexible film; and a plurality of unit cells formed on the flexible film, in which each of the plurality of unit cells includes an IC for adjusting a reflection phase, a line pattern for driving the IC, and first and second antenna patterns formed symmetrically to each other based on the IC or the line pattern.

Abstract: A power transmitting method of a wireless communication system includes a metasurface. The method includes transmitting power of a power supply device to a target device through the metasurface comprising N cells, where N is an integer; estimating, by the metasurface, a channel between the metasurface and the target device based on the power received by the target device and a property matrix with a magnitude of (N+1)×(N+1); adjusting, by the metasurface, a phase of each cell of the N cells based on the estimated channel; and reflecting, by the metasurface, the power transmitted from the power supply device to the target device using the adjusted phase of each cell of the N cells. The property matrix includes information indicating whether each cell of the N cells is turned on and information about a bias value of the wireless communication system.

Abstract: A power transmitting method of a wireless communication system includes a metasurface. The method includes transmitting power of a power supply device to a target device through the metasurface comprising N cells, where N is an integer; estimating, by the metasurface, a channel between the metasurface and the target device based on the power received by the target device and a property matrix with a magnitude of (N+1)×(N+1); adjusting, by the metasurface, a phase of each cell of the N cells based on the estimated channel; and reflecting, by the metasurface, the power transmitted from the power supply device to the target device using the adjusted phase of each cell of the N cells. The property matrix includes information indicating whether each cell of the N cells is turned on and information about a bias value of the wireless communication system.

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Abstract: A roll blind for a vehicle, including: a guide frame formed in an inner circumference of an opening formed in a sun roof of the vehicle; a fixing shaft fixed to either of anterior and posterior areas of the vehicle on the guide frame; an opening shaft disposed on the other one of the anterior and posterior areas to which the fixing shaft is fixed; a blind disposed to selectively cover the opening according to a sliding operation of the opening shaft; and a pressing unit disposed between the fixing shaft and the opening shaft, sliding along the guide frame, rolling a central portion of the blind upward from an upper side of the blind in right and left directions of the vehicle, simultaneously wrapping two sides of the blind and simultaneously providing tension to the blind that moves from the anterior and posterior areas.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.

Abstract: Methods of forming a metal silicide layer are provided that include exposing polysilicon through just dry etching (JDE) and recessesing an oxide layer through chemical dry etching (CDE). In particular, dry etching is primarily performed to an extent to expose the polysilicon. Then, CDE is secondarily performed to expose the polysilicon. The CDE process includes selecting an etchant source among combinations of NF3 and NH3, HF and NH3, and N2, H2, and NF3, dissociating the etchant source, forming an etchant of NH4F and NH4F.HF through the dissociation, producing solid by-products of (NH4)2SiF6 through the reaction between the etchant and an oxide at a low temperature, and annealing the by-products at a high temperature such that the by-products are sublimated into gas-phase SiF4, NH3, and HF.

Abstract: The present invention provides a roll blind for a vehicle, comprising: a guide frame formed in an inner circumference of an opening formed in a sun roof of the vehicle; a fixing shaft fixed to either of anterior and posterior areas of the vehicle on the guide frame; an opening shaft disposed on the other one of the anterior and posterior areas of the vehicle to which the fixing shaft is fixed, the opening shaft sliding along the guide frame in a forward/backward direction of the vehicle; a blind, of which both ends are fixed to the opening shaft and the fixing shaft and which is disposed to selectively cover the opening according to a sliding operation of the opening shaft; and a pressing unit disposed between the fixing shaft and the opening shaft, sliding along the guide frame, rolling a central portion of the blind upward from an upper side of the blind in right and left directions of the vehicle, simultaneously wrapping two sides of the blind and simultaneously providing tension to the blind that moves fr

Abstract: Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.

Abstract: Methods of forming a metal silicide layer are provided that include exposing polysilicon through just dry etching (JDE) and recessesing an oxide layer through chemical dry etching (CDE). In particular, dry etching is primarily performed to an extent to expose the polysilicon. Then, CDE is secondarily performed to expose the polysilicon. The CDE process includes selecting an etchant source among combinations of NF3 and NH3, HF and NH3, and N2, H2, and NF3, dissociating the etchant source, forming an etchant of NH4F and NH4F.HF through the dissociation, producing solid by-products of (NH4)2SiF6 through the reaction between the etchant and an oxide at a low temperature, and annealing the by-products at a high temperature such that the by-products are sublimated into gas-phase SiF4, NH3, and HF.

Abstract: A wiring structure of a semiconductor device comprises an insulating interlayer, a plug and a conductive pattern. The insulating interlayer has an opening therethrough on a substrate. The plug includes tungsten and fills up the opening. The plug is formed by a deposition process using a reaction of a source gas. A conductive pattern structure makes contact with the plug and includes a first tungsten layer pattern and a second tungsten layer pattern. The first tungsten layer pattern is formed by the deposition process. The second tungsten layer pattern is formed by a physical vapor deposition (PVD) process.